Serial Parity Error Circuit Without Reset Signal Latency
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Solution Overview
Problem
Conventional parity error detecting circuits experience latency and require additional devices for reset signals, especially at high data transmission speeds, due to the need for clock signal division and reset operations, which complicates parity error detection.
Innovation Solution
A parity error detecting circuit comprising a first operation unit with an XOR gate and flipflop for initial logic operations, a shift register for signal shifting, and a second operation unit with another XOR gate and flipflop for subsequent logic operations, eliminating the need for reset signals by using clock signals derived from the initial clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional parallel parity error detecting circuit is used, then the parity error detection can be performed, but the latency increases due to the need for clock signal division and reset operations
Solution Approach 1:
The patent extracts and eliminates the reset signal generation mechanism from the parity error detection circuit. By removing the need for reset operations and clock signal division, the circuit achieves continuous operation without the time penalties associated with initialization sequences, thereby reducing latency while maintaining detection reliability
Solution Approach 2:
The circuit performs preliminary XOR operations on incoming serial data bits before requiring any reset or initialization. The accumulated XOR results are maintained in flip-flops and continuously updated, allowing the circuit to be ready for the next data frame without waiting for reset signals, thus reducing detection latency
2Device complexity
If a conventional serial parity error detecting circuit is used, then the circuit structure is simplified, but additional devices are required for generating reset signals
Solution Approach 1:
The patent removes the reset signal generation devices from the circuit architecture. By designing the circuit to operate without reset operations, components dedicated to reset signal generation and distribution are eliminated, reducing the total device count while maintaining structural simplicity
Solution Approach 2:
The clock signal serves multiple functions simultaneously: it drives the serial-to-parallel conversion, clocks the XOR accumulation operations, and enables the output stage. This multi-functionality eliminates the need for separate reset signal paths and associated control devices, reducing overall circuit complexity
3Reliability
If the number of logic circuits is increased to handle more data bits, then the parity error detection coverage is improved, but the propagation delay increases
Solution Approach 1:
The circuit processes data bits in periodic cycles synchronized with the clock signal. Each clock cycle processes one data bit through the XOR accumulation chain, and the results are shifted out systematically. This periodic processing allows the circuit to handle multiple bits without requiring all XOR gates to operate simultaneously, reducing propagation delay while maintaining comprehensive error detection coverage
Solution Approach 2:
The parity detection process is segmented into sequential stages corresponding to individual data bits. Each XOR gate processes one bit position, and the results are accumulated and shifted through dedicated flip-flops. This segmentation allows the circuit to scale to more bits without proportionally increasing the critical path delay, as each stage operates independently in sequence
Data Source
AI summary
A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result of the logic operation as the first signal in response to a first clock signal. The shift register shifts the first signal in response to the first clock signal and outputs a second signal. The second operation unit receives the first signal and the second signal, performs a logic operation on the two received signals, and outputs the result of the logic operation in response to a second clock signal.