Serial Interconnect PHY Timing for Deterministic Low-Latency Links
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and power efficiency, particularly in servers and mobile devices, as they become more complex and require higher performance with minimal power consumption.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that includes a layered protocol stack with a transaction layer, link layer, and physical layer, supporting point-to-point links and virtual channels, and utilizing power management and fault handling mechanisms to optimize data transfer and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then electrical communication is simplified, but bandwidth and communication speed are insufficient for high-performance computing
Solution Approach 1:
The patent segments the interconnect architecture into multiple point-to-point links instead of using a single multi-drop bus. Each link operates independently at higher speeds, allowing parallel communication channels that collectively provide greater bandwidth while maintaining electrical communication simplicity through standardized link interfaces.
Solution Approach 2:
The patent transitions from a single-dimensional multi-drop bus topology to a multi-dimensional mesh-like interconnect fabric with multiple point-to-point links. This dimensional expansion allows data to travel through multiple parallel paths, dramatically increasing communication speed and bandwidth while distributing the complexity across many simple link modules.
2Productivity
If multiple physical processors and cores are added to increase computing power, then processing capacity is improved, but communication between sockets and devices becomes more critical and complex
Solution Approach 1:
The patent implements a universal point-to-point link interface that can connect any processor socket to any device or socket. This multi-functional link design handles various communication types (memory access, I/O operations, processor-to-processor communication) through a single standardized interface, reducing communication complexity despite increasing the number of processing elements.
Solution Approach 2:
The patent introduces link layer protocols and control mechanisms as intermediaries between multiple physical processors and devices. These intermediaries manage communication routing, error handling, and protocol conversion, allowing multiple sockets to communicate efficiently without directly managing the complexity of peer-to-peer interactions.
3Productivity
If interconnect bandwidth is increased to meet demand, then data transfer capability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic link activation where point-to-point links are activated only when needed for specific transactions. Instead of maintaining all interconnect paths at full speed continuously, the system dynamically enables and disables links based on actual communication demands, providing high data transfer capability when required while minimizing power consumption during idle periods.
Solution Approach 2:
The patent changes operational parameters of the interconnect links, transitioning between different power states and speed modes. Links can operate at full speed for high-performance transactions, reduce to lower speeds for routine communication, or enter low-power states when idle, thereby achieving high data transfer capability while optimizing power consumption through parameter adjustment.
Data Source
AI summary
A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.