Serial Interface Rate Negotiation Using Single-Bit Transition Detection
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Solution Overview
Problem
High-speed serial interfaces in programmable logic devices (PLDs) require protocol-dependent logic for rate negotiation, making it challenging to determine data rates independently of the protocol and other PLD components.
Innovation Solution
The method involves using existing clock data recovery (CDR) circuitry and transition-rich encoding schemes like 8B/10B to detect single-bit transitions within a predetermined interval, allowing for independent rate negotiation between full-rate and half-rate modes, and extending to other rate multiples, by integrating a bang-bang phase detector with rate negotiation circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If protocol-specific logic is used for rate negotiation, then rate determination can be made, but device complexity increases and protocol independence is lost
Solution Approach 1:
The patent applies universality by creating a rate negotiation mechanism that works across multiple protocols without requiring protocol-specific logic. The system uses a universal approach of monitoring single-bit transitions and counting them within a predetermined interval to determine data rates, making it applicable to Gigabit Ethernet, Serial ATA, Fibre Channel, and other high-speed serial protocols without modification.
Solution Approach 2:
The patent extracts the rate determination function from protocol-specific logic and implements it independently using only the CDR circuitry and transition counting. By separating the rate negotiation function from protocol-dependent logic, the system achieves protocol independence while maintaining accurate rate determination through the extracted transition counting mechanism.
2Extent of automation
If protocol-dependent logic is integrated into PLD, then rate negotiation is possible, but adaptability to different protocols decreases
Solution Approach 1:
The patent creates a universal rate negotiation mechanism that automatically determines data rates across multiple protocols without requiring protocol-specific configuration or logic. The same transition counting circuitry and evaluation logic are used regardless of whether the protocol is Gigabit Ethernet, Serial ATA, Fibre Channel, or others, achieving both automation and protocol independence.
Solution Approach 2:
The system performs self-service by automatically determining its own data rate through transition counting without requiring external protocol-specific logic or manual configuration. The CDR circuitry and transition counter work together autonomously to negotiate the rate, making the system adaptable to different protocols while maintaining full automation.
3Adaptability or versatility
If transition counting is used for rate detection, then protocol-independent operation is achieved, but measurement precision may be affected
Solution Approach 1:
The patent uses feedback by monitoring the output of the CDR circuitry and using transition count information to determine the actual data rate. The system continuously monitors single-bit transitions during a predetermined interval and uses this feedback to accurately distinguish between full-rate and half-rate operation, maintaining measurement precision while achieving protocol independence.
Solution Approach 2:
The patent changes the measurement parameter from protocol-specific signal analysis to universal transition counting. By measuring the number of single-bit transitions within a predetermined time interval rather than analyzing protocol-specific signals, the system achieves protocol independence while maintaining accurate rate detection through the physical characteristic of data transitions that is common to all serial protocols.
Data Source
AI summary
Automatic rate negotiation logic for a high speed serial interface in a programmable logic device determines whether multiple occurrences of a single-bit transition (i.e., a data transition from “0” to “1” to “0” or from “1” to “0” to “1”) occur within a predetermined time interval on a data channel of a high-speed serial interface. The interval preferably is selected such that multiple occurrences of a single-bit transition mean that the data channel is operating in full-rate mode. The rate negotiation logic may share a phase detector with clock data recovery circuitry in the interface. The phase detector may be a bang-bang phase detector specially adapted to detect single-bit transitions.