Serial Receiver Burst-Gap Control for Fast Signal Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-speed serial communication systems, signal processing circuitry in serial receivers de-tunes during inter-burst gaps, leading to errors in data recovery due to noise compensation, especially in point-to-multipoint communications where transmission intervals are unused, causing prolonged gaps that hinder timely recovery of serial signal bursts.
Innovation Solution
Embedding synchronization information about the start and duration of inter-burst gaps in a control signal from the MAC layer to the PHY layer, allowing the signal processing circuitry to maintain its configuration during these gaps, thus preventing de-tuning and enabling fast reconfiguration upon receipt of new bursts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal processing circuitry continuously compensates for noise during inter-burst gaps, then noise compensation is maintained, but the circuitry de-tunes and cannot recover timely for new bursts
Solution Approach 1:
The patent applies preliminary action by having the signal processing circuitry maintain its configuration state during inter-burst gaps through the pause signal mechanism. Instead of allowing de-tuning to occur and then correcting it, the system proactively preserves the tuned state by interrupting compensation operations during gaps, ensuring readiness for the next burst arrives immediately when data transmission resumes.
2Reliability
If signal processing circuitry operates continuously to clean up serial signal, then signal integrity is maintained, but de-tuning occurs during long inter-burst gaps
Solution Approach 1:
The patent implements periodic action by alternately pausing and resuming signal processing operations based on the burst transmission pattern. The control signal pauses the signal processing circuitry during inter-burst gaps and resumes it when bursts are detected, creating a periodic on-off pattern that matches the transmission schedule. This prevents de-tuning during gaps while ensuring full processing capability is available during actual data transmission periods.
3Productivity
If MAC layer provides detailed burst timing information, then PHY layer can optimize signal processing, but system complexity increases
Solution Approach 1:
The patent extracts only the essential timing information needed for signal processing optimization from the MAC layer. Rather than transmitting complete burst allocation maps or detailed scheduling information, the system extracts and transmits only the critical pause/resume timing signals that the PHY layer needs to maintain optimal configuration. This selective extraction maintains processing efficiency while minimizing added complexity.
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
Various example embodiments of the present disclosure relate to a physical layer, PHY, circuitry for a serial receiver being configured to receive a control signal comprising information indicative for a gap between serial signal bursts from transmitting NTs, for interrupting the operation of its signal processing circuitry in accordance with the information. Other example embodiments relate to a medium access control, MAC, circuitry configured to determine a burst allocation map for network terminals, NTs, and to generate a control signal for a PHY circuitry comprising information indicative for a gap between serial signal bursts from transmitting NTs based on the burst allocation map. Further example embodiments related to a serial receiver, and a method therefor.