Serial Data Receiver Clock Skew Compensation for Lower Bit Errors
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Solution Overview
Problem
High-speed communication channels in integrated circuits face increased bit error rates due to phase differences between data and error clock signals, which can be exacerbated by manufacturing inconsistencies and noise, leading to reduced data transfer bandwidth and higher costs with multiple channels.
Innovation Solution
A receiver circuit with a phase compensation circuit that adjusts the phase difference between data and error clock signals by sampling a reference signal to generate data and error samples, allowing for alignment of sampling transitions and improved bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data rate on a communication channel is increased, then the bandwidth and data transfer capability are improved, but the data window for valid data bits decreases and bit error rate increases
Solution Approach 1:
The patent applies preliminary action by performing channel equalization and sampling clock skew compensation before data sampling. The equalizer pre-compensates for channel distortions, and the phase compensation circuit pre-aligns the sampling clocks, ensuring that when data sampling occurs at high speeds, the data window is already optimized for accurate capture, thereby maintaining low bit error rates despite increased data rates
Solution Approach 2:
The patent implements feedback mechanisms where error samples are used to adjust equalizer coefficients and where phase error detection based on data and error sample comparisons feeds back to adjust sampling clock phases. This closed-loop feedback ensures that as data rate increases, the system continuously adapts to maintain optimal sampling timing and minimize bit errors
2Productivity
If multiple communication channels are used to increase data rate, then the overall bandwidth is improved, but the cost and device complexity increase
Solution Approach 1:
The patent applies universality by designing a single communication channel that performs multiple functions: it carries both data and error samples, and the receiver circuitry handles both equalization and phase compensation. By making the channel multi-functional and the receiver versatile, the system achieves high productivity through optimized single-channel operation rather than requiring multiple separate channels, thereby reducing device complexity
Solution Approach 2:
The patent merges data transmission and error sampling functions into a single communication channel. By combining these functions and using the same physical channel for both purposes, the system achieves high overall data rate without proportionally increasing the number of physical channels, thus avoiding the associated cost and complexity increases
3Reliability
If sampling is performed to determine both data values and error values, then bit error rates are decreased through adjustments, but the device complexity and circuit adjustments increase
Solution Approach 1:
The patent applies segmentation by separating the sampling process into distinct data sampling and error sampling operations using separate sampler circuits. This segmentation allows independent optimization of each sampling path and simplifies the control logic, as each sampler can be independently adjusted based on its specific requirements, thereby managing device complexity while maintaining low bit error rates
Solution Approach 2:
The patent introduces an intermediary phase compensation circuit that mediates between the data sampler and error sampler. This intermediary component handles the complex phase alignment adjustments, isolating the complexity from the main sampling circuits and making the overall system easier to manage while achieving the reliability benefits of adjusted sampling
Data Source
AI summary
An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.