Serial Data Receiver with Dual Trip Points for Lower Bit Error
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Solution Overview
Problem
High-speed serial communication circuits in integrated circuits face challenges with power consumption and bit error rates due to the use of differential amplifiers, which are exacerbated by the need for high data transfer speeds and low voltage levels in mobile computing devices.
Innovation Solution
The implementation of a receiver system with two receiver circuits and a decision circuit that generate data symbols with adjustable valid windows, using different input voltage trip points to extend data valid windows and improve bit error rates without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a differential amplifier is employed to receive high-speed/low voltage signals, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The receiver is divided into two separate receiver circuits, each optimized for different logic transitions. The first receiver circuit handles rising edges with a lower trip point, while the second receiver circuit handles falling edges with a higher trip point. This segmentation allows each circuit to operate more efficiently in its specific transition range, reducing overall power consumption while maintaining high data transfer speeds.
Solution Approach 2:
Each receiver circuit is given different local characteristics through distinct trip points. The first receiver circuit has a lower trip point optimized for detecting rising edges, while the second receiver circuit has a higher trip point optimized for detecting falling edges. This local quality differentiation enables more precise signal detection at lower voltage levels, reducing power consumption without sacrificing speed.
2Reliability
If a differential amplifier with bias voltage generator and reference voltage generator is used, then signal reception capability is improved, but device complexity increases
Solution Approach 1:
The complex differential amplifier is segmented into two simpler receiver circuits, each handling specific logic transitions. This segmentation eliminates the need for complex bias voltage generators and reference voltage generators while maintaining signal reception capability through specialized trip points for each receiver circuit.
Solution Approach 2:
The invention changes the critical parameter from a single differential amplifier configuration to multiple receiver circuits with different trip points. This parameter change simplifies the overall circuit architecture by removing the need for complex voltage generation circuits while maintaining reliable signal reception through optimized transition detection.
3Device complexity
If a single input voltage trip point is used in receiver circuits, then device complexity is reduced, but bit error rate increases due to limited data valid window
Solution Approach 1:
The receiver system is segmented into two receiver circuits, each with a different trip point optimized for specific logic transitions. This segmentation extends the overall data valid window by ensuring that at least one receiver circuit maintains a valid data window throughout the entire transition period, thereby reducing bit errors without significantly increasing complexity.
Solution Approach 2:
Each receiver circuit is assigned a specific local function with a tailored trip point. The first receiver circuit uses a lower trip point for rising edges, while the second uses a higher trip point for falling edges. This local quality optimization ensures that each circuit excels at its specific transition type, collectively providing extended data valid windows and reduced bit error rates.
Data Source
AI summary
An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.