Serial Link Receiver Using Injection-Locked Clock Recovery

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In serial link data transmission, spread-spectrum clocking complicates the tracking of the original clock signal by the receiver, leading to difficulties in accurately recovering the binary data stream due to dispersion in the transmission medium.

Innovation Solution

A serial link receiver apparatus and method that employs a first delay circuit, edge extraction circuit, clock generator, second delay buffer, sampler, and decision circuit to generate a three-phase clock signal, allowing for effective timing recovery by injecting an edge signal into an injection-locked oscillator, which locks the clock signal to the data signal's timing, even with spread-spectrum clocking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If spread-spectrum clocking is used to reduce electromagnetic emission, then electromagnetic compatibility is improved, but clock signal tracking becomes more difficult

Engineering Contradiction:
Improveelectromagnetic emissionVSAvoidclock signal tracking
Core Design Contradiction:
Object-affected harmful factorsVSDifficulty of detecting and measuring

Solution Approach 1:

The patent extracts timing information from the dispersed data signal by detecting edges and using an injection-locked oscillator to recover the clock signal, separating the timing recovery function from the corrupted spread-spectrum clock signal

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an injection-locked oscillator as an intermediary device that uses the dispersed data signal to generate a clean clock signal, mediating between the corrupted transmitted clock and the sampling requirement

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of stationary object

If transmission medium dispersion is present, then signal transmission occurs over distance, but signal quality deteriorates

Engineering Contradiction:
Improvetransmission distanceVSAvoidsignal quality
Core Design Contradiction:
Length of stationary objectVSMeasurement precision

Solution Approach 1:

The patent applies equalization before timing recovery to pre-compensate for dispersion effects, and uses edge detection on the equalized signal to establish timing information before the signal is fully corrupted

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses the recovered timing information to adjust the sampling instant dynamically, creating a feedback loop that compensates for timing drift caused by dispersion in the transmission medium

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Ensures accurate timing recovery and data retrieval by aligning the clock signal with the data signal's transitions, effectively overcoming the challenges posed by spread-spectrum clocking and medium dispersion.

Implementation Method 1

generating a first clock signal based on an injection of the edge signal into an injection-locked oscillator, wherein the first clock signal comprises a plurality of phase clocks

Methodology Applied
Scientific EffectInjection locking:

Data Source

PatentUS8331517B2Serial link receiver and method thereof
Publication Date: 2012.12.11 REALTEK SEMICON CORP
  • US8331517B2 patent drawing
  • US8331517B2 patent drawing
  • US8331517B2 patent drawing

AI summary

A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision.