Serial Receiver Transition Detection for High-Speed Mode Switching
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Solution Overview
Problem
Existing receiver circuits in computing systems struggle to accurately detect and adapt to different modes of communication links, particularly switching between idle and high-speed data modes, leading to potential loss of data and increased latency.
Innovation Solution
A receiver subsystem with signal detection, speed detection, and data receiver circuits that monitor the communication link to detect the presence of high-speed data, activating appropriate subcircuits to prevent data loss by adjusting reference voltages and sampling thresholds based on signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If receiver circuits use fixed detection thresholds and reference voltages, then circuit design is simple, but they cannot accurately detect data mode changes between idle and high-speed modes
Solution Approach 1:
The receiver circuit dynamically adjusts reference voltages and sampling thresholds based on detected signal characteristics. The circuit transitions from static detection parameters to adaptive parameters that change according to the communication mode, enabling accurate detection across different data rates while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent changes detection parameters (reference voltages, sampling thresholds) based on the detected communication mode. During idle mode, one set of parameters is used, while during high-speed data mode, different parameters are applied to optimize detection accuracy for each specific mode.
2Reliability
If receiver circuits activate all subcircuits continuously, then data detection is reliable, but power consumption increases and latency increases during mode switching
Solution Approach 1:
The circuit performs preliminary detection using a simplified detection circuit before fully activating the data receiver circuit. This preliminary action allows the system to prepare for high-speed mode in advance, reducing the latency when actual data reception begins, while maintaining reliable detection through the two-stage approach.
Solution Approach 2:
The receiver circuit dynamically activates or deactivates different subcircuits based on the detected communication mode. During idle mode, only the detection circuit remains active to save power and reduce latency. When high-speed data mode is detected, the data receiver circuit is activated to ensure reliable data reception.
3Use of energy by moving object
If receiver circuits use simplified detection methods, then power consumption is reduced, but data loss may occur during mode transitions
Solution Approach 1:
The detection circuit performs preliminary detection of communication mode changes before the data receiver circuit begins operation. This preliminary action ensures that the system is ready to receive data immediately when high-speed mode starts, preventing data loss during mode transitions while keeping power consumption low during idle periods.
Solution Approach 2:
The detection circuit acts as an intermediary between the communication link and the data receiver circuit. It monitors the communication link for mode changes and triggers the appropriate response, ensuring reliable data reception during mode transitions while maintaining low power consumption during idle mode.
Data Source
AI summary
A serial data receiver subsystem of a computer system includes a data rate detection circuit and a receiver circuit. The data rate detection circuit is configured to detect that a communication link operates in a high-speed mode rather than in a low-speed mode by detecting that a number of transitions in a serial data stream over a reference period of time exceeds a threshold value. The date rate detection circuit is further configured to activate a data rate detection signal indicating that the communication link operates in the high-speed mode, the data rate detection signal activated in response to detection that the number of transitions in the serial data stream over the reference period of time exceeds the threshold value. The receiver circuit is configured to activate one or more of a plurality of subcircuits included in the receiver circuit in response to activation of the data rate detection signal.