Serial Link Receiver Equalization for Low-Voltage Noise Immunity
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Solution Overview
Problem
High-speed serial link receivers face challenges in impedance matching and equalization, particularly with low supply voltage, which limits signal-to-noise ratio and is susceptible to DC offsets, power supply noises, and secondary dispersion.
Innovation Solution
The implementation of a receiver architecture that includes a passive CTLE, CG amplifier, active inductors, and a CS CTLE, along with a decision circuit, to achieve impedance matching and equalization, with control signals adjusting input resistance, gain, and transition frequency to alleviate impairments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a low supply voltage is used to reduce power consumption, then power consumption is reduced, but the signal-to-noise ratio is limited and the receiver becomes more susceptible to noises and impairments
Solution Approach 1:
The patent implements dynamic control of equalization parameters through multiple control signals that adjust the CTLE and CS CTLE circuits in real-time. This allows the receiver to adapt to varying channel conditions and maintain optimal signal-to-noise ratio even at low supply voltages, resolving the contradiction between low power consumption and reliable signal detection
Solution Approach 2:
The patent changes key circuit parameters including impedance values, gain levels, and frequency responses through controlled adjustment of the CTLE and CS CTLE circuits. By dynamically modifying these parameters, the system maintains high signal-to-noise ratio performance while operating at reduced supply voltages, thereby reducing power consumption without sacrificing reliability
2Reliability
If equalization is applied to compensate channel dispersion, then signal detection reliability is improved, but DC offsets, additive noises, nonlinear distortion, and secondary dispersion are introduced
Solution Approach 1:
The patent introduces a carefully designed CTLE circuit as an intermediary between the channel and the decision circuit. This intermediary performs equalization while incorporating specific circuit topologies that minimize the generation of harmful artifacts such as DC offsets and nonlinear distortion, thus maintaining signal detection reliability without introducing excessive impairments
Solution Approach 2:
The patent employs feedback mechanisms where the output of the equalization circuit is monitored and used to adjust the equalization parameters. This feedback loop allows the system to compensate for introduced impairments by dynamically adjusting control signals to the CTLE and CS CTLE circuits, thereby maintaining high detection reliability while minimizing harmful effects
3Reliability
If impedance matching is not achieved at the receiver input port, then dispersion is aggravated due to reflection, but achieving impedance matching increases circuit design complexity
Solution Approach 1:
The patent merges the impedance matching function with the equalization function in a unified CTLE circuit design. By combining these two functions into a single integrated circuit rather than implementing them as separate stages, the patent achieves effective impedance matching and dispersion compensation while minimizing the increase in circuit design complexity
Data Source
AI summary
A receiver includes a passive CTLE (continuous-time linear equalizer) configured to receive a first voltage signal from a first node and output a current signal to a second node in accordance with a first control signal; a CG (common-gate) amplifier configured to receive the current signal and output a second voltage signal at a third node in accordance with a second control signal; a first active inductor configured to provide an inductive load at the third node; a CS (common-source) CTLE configured to receive the second voltage signal and output a third voltage signal at a fourth node in accordance with a third control signal; a second active inductor configured to provide an inductive load at the fourth node; and a decision circuit configured to receive the third voltage signal and output a decision in accordance with a clock signal.