Serial Data Receiver Using Reference Voltage Control for Baud-Rate CDR
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Solution Overview
Problem
Current systems for serial data transmission, particularly in baud-rate receivers, face challenges in effectively controlling the parameters of clock and data recovery circuits (CDR) and continuous time linear equalizers (CTLE), which can lead to inaccuracies in clock signal and data restoration, especially in channels with frequency-dependent attenuation.
Innovation Solution
A system and method that includes a baud-rate CDR and a reference voltage control circuit, which uses adjustable reference voltages to align clock phase errors and control the CTLE parameters, eliminating the need for phase interpolators and allowing for accurate clock and data recovery without multiple clock phases, and an equalizer control circuit that adjusts parameters to minimize bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If baud-rate receiver uses single clock phase, then device complexity is reduced by eliminating phase interpolators, but measurement precision of clock phase alignment deteriorates
Solution Approach 1:
The patent changes the control parameter from multiple clock phases to adjustable reference voltages. The reference voltage control circuit dynamically adjusts reference voltages to align clock phase errors, achieving precise clock phase alignment without requiring phase interpolators or multiple clock phases, thus resolving the contradiction between device complexity and measurement precision
Solution Approach 2:
The patent introduces an intermediary reference voltage control circuit that mediates between the clock signal and the sampling process. This circuit adjusts reference voltages to compensate for clock phase errors, enabling precise timing alignment without direct phase interpolation, thereby maintaining measurement precision while reducing device complexity
2Adaptability or versatility
If reference voltages are controlled by external circuits, then adaptability to different channels is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent merges the reference voltage control function with the existing CDR and equalizer control circuits. The reference voltage control circuit is integrated into the signal processing path, sharing control logic and resources with other circuits, thereby achieving channel adaptability without proportionally increasing device complexity
Solution Approach 2:
The reference voltage control circuit is designed with multi-functionality, serving both as a CDR parameter controller and an equalizer parameter controller. This universal circuit adjusts parameters for both CDR and CTLE based on channel conditions, achieving high adaptability while minimizing additional circuit complexity through resource sharing
3Measurement precision
If CTLE parameters are controlled adaptively, then measurement precision of signal recovery is improved, but device complexity increases due to equalizer control circuit
Solution Approach 1:
The patent implements feedback control where the equalizer control circuit continuously monitors signal quality metrics and adjusts CTLE parameters accordingly. This feedback mechanism enables adaptive signal recovery precision by dynamically optimizing equalizer settings based on actual channel conditions, achieving high measurement precision while keeping the control circuit relatively simple through efficient feedback loops
Data Source
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AI summary
A circuit for receiving serial data. In some embodiments, the circuit has an input for receiving an analog input signal, and includes a first sampler for sampling the analog input signal relative to a first reference voltage, a second sampler for sampling the analog input signal relative to a second reference voltage, and a reference voltage control circuit. The second reference voltage may have a sign opposite to that of the first reference voltage; and the reference voltage control circuit may be configured to adjust the first reference voltage or the second reference voltage, based on a first sample of the analog input signal, the first sample having been taken at a sampling time corresponding to a one bit, in the serial data, preceded by a one bit and followed by a one bit.