Serial Reception Circuit Multiphase Sampling Jitter Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in suppressing bit errors due to long-period jitter in high-speed serial transmission, particularly in mobile terminals where power consumption is a concern, as conventional methods require multiple VCOs and complex circuit configurations to maintain phase accuracy across varying communication protocols and transmission path characteristics.
Innovation Solution
A serial reception circuit that employs multiphase sampling clock signals to determine an optimum sampling phase with reduced sampling operations, incorporating a first mode for initial phase detection and a second mode for phase tracking, which allows for dynamic phase updates and reduced power consumption by disabling unnecessary clock signals, thereby addressing long-period jitter and supporting multiple communication protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase synchronization method using PLL is used to synchronize with serial data, then phase accuracy is improved, but the reception start time is delayed and power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing phase detection before formal data reception using a detection period where the sampling clock is advanced relative to the data clock. This allows the system to pre-determine the optimal sampling phase relationship, enabling immediate data reception without the synchronization delay inherent in PLL methods. The phase detection unit operates in advance to establish the phase offset that will be used during subsequent data reception.
Solution Approach 2:
The patent segments the reception process into distinct phases: a detection period for phase determination and a data reception period for actual communication. During the detection period, the system separately measures phase relationships without processing actual data, then uses this information during the reception period. This segmentation allows the system to achieve fast synchronization without compromising data reception performance.
2Adaptability or versatility
If multiple VCOs are mounted to support multiple differential links, then phase synchronization capability is improved, but total power consumption increases
Solution Approach 1:
The patent implements universality by using a single detection unit that can service multiple differential links rather than dedicating a VCO to each link. The phase detection mechanism is designed to be shared across multiple reception circuits, allowing one detection unit to determine optimal phases for multiple data clocks. This multi-functional approach enables multi-link support while avoiding the power consumption penalty of multiple VCOs.
Solution Approach 2:
Instead of using expensive VCOs for each link, the patent uses a simplified detection unit that copies or replicates the phase detection function across multiple links. The detection unit generates phase information that can be applied to multiple differential links, effectively copying the synchronization capability rather than duplicating the full VCO functionality for each link.
3Measurement precision
If pattern matching to unique code is used for phase determination, then synchronization accuracy is improved, but circuit configuration complexity increases for multiple protocols
Solution Approach 1:
The patent replaces the mechanical approach of pattern matching with a signal processing approach using correlation detection. Instead of comparing sampled data against predefined unique codes for each protocol, the system uses a correlation unit to measure the correlation between the received signal and a reference signal. This substitution eliminates the need for protocol-specific pattern matching circuits while maintaining synchronization accuracy through mathematical correlation operations.
Data Source
AI summary
There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.