Serial Data Sampling With Supplemental Clock Majority Decision
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Solution Overview
Problem
UART serial communication devices face errors due to mismatches in data communication speed and sampling clock cycles, leading to noise-induced detection errors, and existing solutions burden the system with software processing and circuit requirements.
Innovation Solution
A serial communication device that generates a supplemental clock at adjustable timings between communication clocks, allowing data to be sampled at multiple timings and decided by majority, minimizing timing shifts and enhancing noise resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling clock cycle is set according to a predetermined specification, then the communication speed matching is improved, but the timing shift between sampling clock and serial data increases due to cycle errors
Solution Approach 1:
The patent introduces a dynamic timing adjustment mechanism that allows the sampling clock timing to be flexibly adjusted based on detected timing shifts. The sampling timing is no longer fixed to a predetermined specification but can be dynamically corrected to maintain synchronization with the serial data, resolving the contradiction between initial precision and ongoing reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the timing relationship between the sampling clock and serial data is continuously monitored, and timing adjustments are made based on detected errors. This closed-loop control ensures that timing synchronization is maintained despite initial cycle errors, improving reliability while preserving measurement precision.
2Adaptability or versatility
If software processing is used to change sampling clock timing, then the timing adaptability is improved, but the system complexity and processing burden increase
Solution Approach 1:
The patent replaces software-based timing adjustment with a hardware-level timing correction mechanism. By implementing timing adjustment in the hardware domain rather than through software processing, the system achieves high timing adaptability while reducing processing burden and overall system complexity.
Solution Approach 2:
The timing adjustment mechanism operates autonomously at the hardware level, automatically detecting and correcting timing shifts without requiring software intervention. This self-service approach provides adaptability while eliminating the processing burden that would otherwise be imposed on the software system.
3Reliability
If multiple communication clocks are used for 1-bit data transfer to achieve noise resistance, then the noise resistance is improved, but the sampling period increases and timing shift influence increases
Solution Approach 1:
The patent dynamically adjusts the sampling timing within the available window to optimize the balance between noise resistance and sampling period. By flexibly positioning the sampling point rather than using fixed multiple sampling cycles, the system maintains noise resistance while minimizing the sampling period and reducing timing shift influence.
Solution Approach 2:
The patent performs preliminary timing adjustment to optimize the sampling point before actual data sampling occurs. This preliminary action allows the system to prepare the optimal sampling timing that achieves noise resistance with minimal sampling period, preventing the need for extended multiple-clock sampling.
Data Source
AI summary
The invention is a serial communication device for receiving serial data and sampling the serial data with synchronizing with communication clocks. The device has a clock generation unit for dividing a reference clock according to a predetermined dividing value, generating the communication clock each time the number of dividing value of the reference clock is generated, and generating a supplemental clock at any timing of the reference clock between adjacent communication clock; and a data decision circuit for receiving serial data, sampling 1-bit data at sampling timings including at least the adjacent communication clocks and the supplemental clock therebetween, and deciding the 1-bit data according to the decision by majority of the plurality of the sampling data which is sampled.