Serial Shift Register Decoder for Hashing Address Traversal
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Solution Overview
Problem
Existing technologies face challenges in efficiently traversing a 2N-sized address space in a non-incremental fashion without using addition or multiplication, particularly in hardware implementations of hashing tables, where traditional methods are inefficient due to the need for prime numbers and complex operations.
Innovation Solution
A method using a serial shift register decoder that generates addresses by successively choosing between double the current number and double the number plus one, with the least-order bit defining connections in a circular shift register, allowing for non-incremental traversal of a 2N address space through a single bit shift and low-order bit insertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional parallel decoding is used after serial loading, then address data can be decoded, but access time is increased due to the delay of parallel decode and word access after the last external bit is available
Solution Approach 1:
The patent replaces the traditional mechanical approach of serial loading followed by parallel decoding with a direct serial decoding mechanism. The decoder processes address bits sequentially as they arrive from the serial interface, eliminating the need to wait for all bits to be loaded before decoding can begin. This substitution of the decoding mechanism itself resolves the time delay issue.
2Productivity
If the address is broken into high- and low-order bits with high-order bits loaded first, then data can be available on multiplexer inputs earlier, but additional registers and complex timing are required
Solution Approach 1:
The patent merges the functions of address registration and decoding into a single serial decoding unit. Instead of separating high-order and low-order address bits into different registers and using multiplexers to combine them, the invention processes the complete address sequentially through a unified decoder structure, eliminating the need for separate registers and multiplexer logic.
Solution Approach 2:
The serial decoder is designed to handle the entire address decoding function universally, processing any address bits in sequence regardless of their positional significance. This multi-functional approach eliminates the need for specialized high-order and low-order address handling circuits, simplifying the overall device structure while maintaining high-speed performance.
3Ease of operation
If hashing tables use prime number locations and incremental traversal, then all entries can be accessed, but the number of accesses increases and performance decreases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimized non-incremental step values in a step table during system initialization. These step values are computed offline to ensure complete coverage of all hash table entries. During runtime, the serial decoder simply follows these pre-determined steps, eliminating the need for runtime calculations and minimizing the number of memory accesses required to traverse the entire table.
Data Source
AI summary
A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.