Serial Shift Register Decoder for Memory Testing
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Solution Overview
Problem
Existing memory testing techniques are inefficient, particularly in selecting all address lines and requiring comparison logic at each address, which is not readily available in standard memories, and struggle with testing large memories due to high latency and cost considerations.
Innovation Solution
A method utilizing a serial shift register decoder to simultaneously write and read memory words, employing partial address decoding and rotation to efficiently test memories by selecting multiple words in fewer cycles, and using output logic to detect mid-voltage faults indicative of memory errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all address lines are selected simultaneously for memory testing, then test coverage is improved, but test time and complexity increase significantly
Solution Approach 1:
The patent segments the address space into multiple banks, where each bank can be independently selected and tested. Instead of selecting all addresses simultaneously, the system divides the memory into manageable segments (banks) that can be tested in parallel or sequence, reducing the overall test time while maintaining comprehensive coverage.
Solution Approach 2:
The patent implements periodic action through cyclic bank selection, where different banks are selected in a repeating cycle. This allows the testing process to systematically cover all address spaces over multiple cycles, ensuring complete test coverage while distributing the test workload over time rather than requiring all addresses to be tested simultaneously.
2Measurement precision
If comparison logic is added at each memory address for simultaneous testing, then test accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the comparison function from individual memory locations and consolidates it into a centralized comparator unit. Instead of having comparison logic distributed at each address, the system uses a single comparator that receives data from selected banks and performs comparisons externally, significantly reducing the complexity and cost of the memory device while maintaining test accuracy.
Solution Approach 2:
The patent introduces an intermediary comparator unit that acts as a mediator between the memory banks and the test system. This external comparator performs the comparison function without being integrated into the memory device itself, allowing accurate testing while keeping the memory device simple and cost-effective.
3Productivity
If serial address decoding is used to reduce test time, then productivity is improved, but latency increases
Solution Approach 1:
The patent applies preliminary action by pre-loading the serial shift register with address bits before the actual memory access occurs. The address decoding process begins in advance, with each clock cycle advancing the decoding state, so that by the time the memory access is needed, the correct bank is already selected and ready, minimizing the impact of serial decoding on access latency.
Data Source
AI summary
Testing of memories that decode a serial stream of address data to access the memory may be performed by cither successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.