Serial Communication Skew Adjustment via Header-Based Lane Synchronization

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Solution Overview

Problem

In high-speed serial communication systems, particularly in production printing, there is a timing lag between serial data transferred via multiple routes due to data transfer delays, leading to reduced data transfer efficiency and increased circuit complexity in synchronization techniques like Japanese Patent No. 6531513, which adds frames to data for synchronization.

Innovation Solution

A serial communication apparatus and method that divides transmission data into equal parts across multiple lanes, adds header information, and uses a received packet skew adjusting unit to synchronize data by detecting header information and writing data to a buffer only when a predetermined number of cycles are completed, allowing for efficient skew adjustment and transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data transmission start frame and data transmission completion frame are added to synchronize serial data via multiple routes, then synchronization between lanes is achieved, but effective transfer efficiency of data is reduced

Engineering Contradiction:
Improvesynchronization between lanesVSAvoideffective transfer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the synchronization function from the data stream by using dedicated header information that indicates packet boundaries and lane assignment. This allows synchronization to be achieved through detecting these headers rather than adding separate start and completion frames to each data packet, thereby reducing overhead and improving effective transfer efficiency while maintaining lane synchronization.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary action by pre-defining header information structure that contains lane identification and packet boundary markers before data transmission begins. The receiving side uses these pre-defined headers to proactively identify and synchronize data from multiple lanes without requiring reactive frame-based synchronization, thus improving efficiency.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data transmission start frame and data transmission completion frame are added to synchronize serial data, then lane synchronization is achieved, but circuit scale of reception processing circuit is increased

Engineering Contradiction:
Improvelane synchronizationVSAvoidcircuit scale of reception processing circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential synchronization information into compact header fields within the data stream itself, rather than requiring separate control frames. The reception processing circuit only needs to detect and parse these headers to achieve lane synchronization, significantly reducing circuit complexity compared to implementing full frame-based synchronization with start and completion detection.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the synchronization approach from frame-based temporal parameters to header-based structural parameters. By embedding lane identification and boundary markers as fixed-format header information, the reception circuit can use simple pattern matching and counter operations instead of complex frame detection logic, reducing circuit scale.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If complicated control is performed to detect start frame, store data in buffer, and transfer after skew removal, then synchronization is achieved, but reception processing circuit complexity increases

Engineering Contradiction:
Improvedata synchronizationVSAvoidreception processing circuit control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts synchronization control information into dedicated header fields that are automatically detected during data reception. This eliminates the need for complex multi-step control processes including start frame detection, buffer management, and skew removal sequencing. The header information directly provides lane identification and packet boundaries, simplifying the control logic to basic header parsing and data forwarding operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11777627B2Serial communication apparatus and serial communication method that are capable of efficiently eliminating a timing lag between serial, data transferred via a plurality of routes in serial communication
Publication Date: 2023.10.03 CANON KK
  • US11777627B2 patent drawing
  • US11777627B2 patent drawing
  • US11777627B2 patent drawing

AI summary

A serial communication apparatus capable of efficiently eliminating a timing lag between serial data transferred via a plurality of routes in serial communication is provided. The serial communication apparatus transfers serial data transmitted from a transmitting side communication unit disposed on a transmitting side to a receiving side communication unit disposed on a receiving side via a plurality of lanes. The transmitting side communication unit comprises a packet transmitting unit configured to divide transmission data into equal parts according to the number of the lanes, distribute the divided transmission data to each lane as a data main body, and add header information indicating the type of the transmission data to the divided transmission data distributed to each lane. The receiving side communication unit comprises a received packet skew adjusting unit configured to adjust skew of data received in each lane.