Serial-Stack Flip-Flop Precharge for Low-Glitch Signal Transmission
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Solution Overview
Problem
In high-integration integrated circuits, the increased computations in combinational logic circuits lead to delays in output transmission from sequential circuits, resulting in power consumption issues due to glitch generation from the speed of discharging static circuits.
Innovation Solution
A flip flop design incorporating a serial stack structure of PMOS transistors in the precharge circuit and NMOS transistors in the discharge circuit, along with keeper circuits to maintain voltage levels, reduces glitch generation by optimizing the charging and discharging process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a semi-dynamic flip flop is used to reduce delay time in high integration circuits, then the output transmission speed is improved, but glitches are generated due to speed mismatch in discharging the static circuit, causing increased power consumption
Solution Approach 1:
The patent segments the precharge and discharge functions into separate dedicated circuits. The precharge circuit includes separate PMOS transistors for precharging the first node, while the discharge circuit includes separate NMOS transistors for discharging the first node and second node. This segmentation allows independent optimization of precharge and discharge speeds, preventing glitches caused by speed mismatch while maintaining high transmission speed.
Solution Approach 2:
The precharge circuit performs preliminary charging of the first node before the discharge operation. By precharging the first node to a stable voltage level in advance, the circuit ensures that when discharge occurs, there is no voltage level conflict or glitch. The keeper circuit also maintains the voltage level of the second node in advance to prevent unwanted transitions.
2Speed
If the static circuit discharges quickly to improve response time, then the speed is improved, but glitches are generated due to speed mismatch, increasing power consumption
Solution Approach 1:
The discharge function is segmented into two independent discharge circuits: one for discharging the first node (including first and second NMOS transistors) and another for discharging the second node (including third and fourth NMOS transistors). This segmentation allows each discharge path to be independently controlled and optimized, preventing speed mismatch glitches while maintaining fast discharge response.
Solution Approach 2:
The keeper circuit acts as an intermediary between the discharge circuits and the output. It maintains the voltage level of the second node and prevents direct coupling between the discharge operations, thereby eliminating glitch generation caused by speed mismatch while allowing both nodes to discharge quickly.
3Object-generated harmful factors
If more transistors are added to optimize charging and discharging to reduce glitches, then glitch generation is reduced, but device complexity increases
Solution Approach 1:
The patent extracts the glitch-generating elements (the speed mismatch between precharge and discharge operations) and separates them into independent circuits with dedicated control. By taking out the problematic interaction and placing precharge and discharge functions in separate circuits with separate transistor sets, the design reduces glitches while keeping each individual circuit relatively simple and manageable.
Data Source
AI summary
A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.