Serial Data Stream Circuit With Embedded Clock and Start Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data transmission systems are complex to implement due to the need for separate lines and signal processing for clock signals and start information, leading to increased wiring complexity and logic complexity in identifying the position of useful data bits within serial data streams.
Innovation Solution
A circuit arrangement that includes an input circuit to read a serial data stream, a data processing circuit to remove a useful data bit at a prescribed position after the start of the stream, and an output circuit to output the stream with the removed bit omitted, allowing for reduced wiring complexity by integrating clock and start information within the data stream.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate lines and signal processing are used for clock signals and start information, then data transmission reliability is improved, but wiring complexity increases
Solution Approach 1:
The patent combines clock signals, start information, and data bits into a single serial data stream. The most significant bit (MSB) of each data byte serves as the clock signal, while the least significant bit (LSB) indicates the start of data transmission. This merging eliminates the need for separate clock and start signal lines, reducing wiring complexity while maintaining transmission reliability through integrated signal processing.
2Reliability
If separate lines and signal processing are used for clock signals and start information, then data transmission reliability is improved, but logic complexity increases
Solution Approach 1:
The patent implements a universal data bit structure where each bit in the serial stream serves multiple functions. The MSB functions as both data and clock signal, while the LSB serves as both data and start indicator. This multi-functionality reduces the need for separate logic circuits for clock synchronization and start detection, thereby reducing logic complexity while ensuring reliable data transmission.
3Device complexity
If data bits are transmitted in serial fashion with integrated clock and start information, then wiring complexity is reduced, but the ability to identify data bit positions becomes more difficult
Solution Approach 1:
The patent uses bit position encoding where specific positions in the serial stream have defined meanings. The MSB position indicates clock synchronization, the LSB position indicates start of data, and intermediate positions contain actual data. This positional encoding scheme allows receiving circuits to easily identify data bit positions by their location in the stream, overcoming the difficulty of position identification while maintaining simplified wiring.
Data Source
AI summary
A circuit arrangement comprises an input circuit for reading in a serial data stream, which comprises a plurality of useful data bits, and for reading in a piece of information which indicates the start of the serial data stream. The circuit arrangement also comprises a data processing circuit for removing at least one useful data bit from the read-in, serial data stream. The data processing circuit is designed such that it removes the at least one useful data bit at a prescribed position after the start of the serial data stream. The circuit arrangement also comprises a first output circuit for outputting the read-in, serial data stream for the omission of the at least one removed useful data bit.