Serial Bit Stream Alignment Using SFD Position Correction
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Solution Overview
Problem
Serializer/deserializer systems face issues with bit shifting and corruption during bit locking, leading to misalignment and loss of frames, especially when the transmit data clock is not in phase with the embedded serial data clock, causing DPLL to miss or gain bits, resulting in bit shifting or corruption of the preamble.
Innovation Solution
A method and circuit that latch Q bits from the serial bit stream, locate the position of the first bit of the Start of Frame Delimiter (SFD), and discard P-1 bits to align the serial bit stream with the parallel output, utilizing fault-tolerant analysis logic to correct for bit shifts and corruption, ensuring accurate frame recognition and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DPLL synchronizes the transmit data clock with the embedded serial data clock during the preamble, then clock synchronization is achieved, but bit shifting occurs causing the DESERDES to miss or gain bits
Solution Approach 1:
The patent applies preliminary action by performing bit alignment correction after clock synchronization is achieved. The DPLL first synchronizes the clocks during the preamble, then the system detects bit shifting and corrects it by identifying the SFD pattern position and discarding the appropriate number of bits. This two-stage approach (first synchronize, then align) resolves the contradiction between achieving clock synchronization and maintaining bit alignment precision.
2Productivity
If the DESERDES reads the bit stream during bit locking, then data transmission continues, but bit corruption occurs in the preamble causing frame loss
Solution Approach 1:
The patent implements feedback by continuously monitoring the received bit stream for the SFD pattern during the bit locking process. When the SFD is detected at the expected position, the system confirms successful frame recognition. If bit corruption occurs, the feedback mechanism detects the misplaced SFD and triggers correction by discarding the appropriate number of bits to realign the frame, thus maintaining reliability while allowing continuous data transmission.
3Measurement precision
If the SFD pattern is used to mark the last two bits of the preamble, then frame delimitation is achieved, but bit shifting causes the SFD position to be misidentified
Solution Approach 1:
The system performs preliminary clock synchronization using the DPLL before attempting to detect the SFD position. This ensures that the bit timing is accurate when searching for the SFD pattern. After detection, if bit shifting is identified, a second correction step discards the appropriate number of bits to realign the SFD position, thus achieving both frame delimitation accuracy and precise SFD position detection despite initial bit shifting.
Data Source
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AI summary
The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-I bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.