Parallel-to-Serial Data Synchronization With Variable Clock Delay
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Solution Overview
Problem
Existing data signal generating apparatuses face challenges in minimizing size due to large delay devices required for timing adjustments and are limited in accurately measuring jitter due to frequency constraints of PLL-controlled output data rates.
Innovation Solution
A data signal generating apparatus that includes a data output unit synchronized with a data synchronization clock, a multiplexer for parallel-serial conversion, and a synchronization means with a phase comparator and variable delay device to synchronize parallel data output with a latch signal, allowing for accurate jitter measurement and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay device is used to adjust timing between parallel data and latch signal, then synchronization is achieved, but the apparatus size increases due to extensive wiring requirements
Solution Approach 1:
The patent applies dynamics by making the delay time variable rather than fixed. The variable delay device adjusts the delay time dynamically based on the actual delay characteristics of the data output unit, allowing precise synchronization without requiring large fixed delay devices or extensive wiring for timing adjustments.
Solution Approach 2:
The patent implements feedback by using a phase comparator to detect the phase difference between the parallel data and latch signal, then using this detection result to control the variable delay device. This closed-loop feedback mechanism enables automatic adjustment of delay time to achieve optimal synchronization, eliminating the need for large margin-based delay devices.
2Productivity
If PLL-controlled frequency division is used to generate data request signals, then data rate control is achieved, but jitter measurement accuracy is limited by the frequency constraints
Solution Approach 1:
The patent introduces an intermediary approach by using a counter to measure the phase difference in terms of clock cycles rather than relying on PLL frequency division. This intermediary measurement method allows jitter measurement at various data rates without being constrained by PLL frequency limits, improving measurement accuracy while maintaining productivity.
3Stability of the object's composition
If fixed delay time is designed into the system, then timing synchronization is achieved, but the system cannot adapt to variations in data output timing
Solution Approach 1:
The patent resolves this contradiction by making the delay time dynamic and adjustable. The variable delay device can adapt its delay time based on actual operating conditions and detected phase differences, maintaining timing stability while providing the flexibility to adapt to variations in data output timing from different memory devices or operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The apparatus ensures stable serial data output in a desired sequence, handles jitter measurement accurately, and maintains a compact size by using a variable delay device to adjust timing without the need for extensive wiring or frequency limitations.
Implementation Method 1
a phase comparator (16) for comparing the phase of the data synchronization clock signal with the phase of the latch signal
Implementation Method 2
a variable delay device (30) for delaying, on the basis of the control signal, the reference clock signal or a divided clock signal
Data Source
AI summary
A data signal generating apparatus with a data output unit for outputting m-bit parallel data and a data synchronization clock signal synchronized with the parallel data in response to a data request signal produced by dividing the frequency of a reference clock signal by “m.” An m:1 multiplexer for receiving the parallel data in response to a latch signal produced by dividing the frequency of the reference clock signal by “m,” and outputting, at a rate of the reference clock signal, data synchronization serial data. Synchronization means for comparing the phases of the data synchronization clock signal and the latch signal, for synchronizing the parallel data with the latch signal, and for producing a control signal, and which delays, on the basis of the control signal, the reference clock signal or a divided clock signal (dividing the frequency of the reference clock signal by “m” or less).