Serial Transceiver Clock Recovery for Low-Jitter Data Synchronization
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Solution Overview
Problem
High-speed serial communication systems face challenges with data skew and jitter due to the need for a reference clock, leading to increased hardware costs and error rates, particularly over long distances and during speed changes.
Innovation Solution
A serial transceiver using a clock recovery circuit with a coarse code generator, frequency detector, and linear phase detector, which eliminates the need for a reference clock and reduces jitter by controlling the voltage controlled oscillator based on data rate and phase synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference clock signal is transmitted simultaneously with data, then synchronization reference is provided for high speed transception, but skew between data and reference clock occurs during long distance transmission
Solution Approach 1:
The patent extracts the clock signal from the transmitted data stream by detecting edges of the data signal itself, rather than transmitting a separate reference clock signal. This eliminates the skew problem between data and clock by deriving the clock purely from the data edges, while still maintaining synchronization accuracy through edge-based clock recovery.
Solution Approach 2:
The patent introduces an embedded clock signal within the data stream that serves as an intermediary between the transmitted data and the receiver's clock recovery mechanism. This embedded clock is extracted from data edges and used to synchronize the receiver without requiring a separate reference clock transmission.
2Reliability
If a reference clock signal is transmitted, then synchronization is maintained, but the number of transmission channels and hardware costs increase
Solution Approach 1:
The patent merges the clock signal with the data signal by embedding clock information within the data stream through edge detection. Instead of using separate transmission channels for data and clock, the system combines them into a single channel, reducing hardware complexity while maintaining synchronization.
Solution Approach 2:
The transmitted data signal serves multiple functions: it carries both the actual data information and the clock synchronization information. By detecting edges of the data signal, the receiver can extract both data and clock from the same channel, making the transmission system more universal and efficient.
3Reliability
If a loaded clock supplier is used in the clock recovery circuit, then clock extraction is improved, but areas, costs, and power are increased
Solution Approach 1:
The clock recovery circuit uses the data signal itself to generate the clock signal through edge detection, rather than relying on an external clock supplier. The system serves itself by extracting clock information from the transmitted data edges, eliminating the need for additional power-consuming clock generation components.
4Adaptability or versatility
If statistical methods are used for data rate detection, then multi-speed embedded clock serial receivers can detect data edges, but jitter of recovered clock signal is higher and speed limitations occur
Solution Approach 1:
The patent implements a dynamic phase detector that continuously adjusts the phase of the recovered clock signal based on the detected data edges. This dynamic adjustment mechanism allows the system to adapt to different data rates while maintaining low jitter by continuously optimizing the clock phase alignment with the incoming data stream.
Data Source
AI summary
A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.