Serial Transceiver Delay Synchronization for Loop Back Testing

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Solution Overview

Problem

In serial transceivers, the variable delay times during loop back tests lead to misjudgment and increased production costs due to the need for complex external circuit checks, which are prone to errors.

Innovation Solution

A serial transceiver with a controlling module that generates a delay time signal based on target, transmitting, and receiving time signals to synchronize package delivery to the data link layer, reducing external circuit influence and ensuring accurate testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If packages are transmitted through external circuits during loop back test, then the serial transceiver can perform testing, but the variable delay times cause misjudgment and reduced test accuracy

Engineering Contradiction:
Improvetest accuracyVSAvoiddelay time consistency
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by introducing a delay adjustment module that pre-calculates and applies compensation for external circuit delay times before the loop back test is performed. This ensures that packages are delayed by a fixed, predetermined amount to compensate for the variable delays introduced by external circuits, thereby achieving consistent and accurate test results without requiring complex real-time adjustments during testing.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If complex external circuit checks are used to verify package transmission, then the serial transceiver can detect transmission status, but the checking mechanism becomes more complex and prone to errors

Engineering Contradiction:
Improvedetection accuracyVSAvoidchecking mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the delay compensation function from the complex external circuit checking mechanism and implements it through a dedicated delay adjustment module. This module independently calculates and applies the necessary delays based on predetermined external circuit characteristics, separating the compensation function from the detection function and simplifying the overall system while improving reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If packages are transmitted at different times through multiple channels, then the serial transceiver can handle multiple data streams, but the variable delay times make it difficult to ensure simultaneous arrival at the data link layer

Engineering Contradiction:
Improvemulti-channel transmission capabilityVSAvoidpackage arrival synchronization
Core Design Contradiction:
ProductivityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by implementing channel-specific delay adjustment for each transmission channel. Each channel has its own delay adjustment mechanism that tailors the delay compensation to that specific channel's external circuit characteristics. This allows multiple channels to transmit packages simultaneously while ensuring that each channel's packages arrive at the data link layer at the correct synchronized time, maintaining both high productivity and arrival synchronization.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7599382B2Serial transceiver and method of transmitting package
Publication Date: 2009.10.06 VIA TECH INC
  • US7599382B2 patent drawing
  • US7599382B2 patent drawing
  • US7599382B2 patent drawing

AI summary

A serial transceiver transmits at least one package of a data link layer and includes at least one channel including at least one transmitting module and at least one receiving module, a generating module and a controlling module. The channel is for transmitting the corresponding package. The transmitting module transmits the corresponding package and generates a transmitting time signal. The receiving module receives the package transmitted from the corresponding transmitting module and generates a receiving time signal. The generating module generates a target delay time signal. The controlling module receives the target delay time signal, transmitting time signals and receiving time signals, and generates a delay time signal for the corresponding receiving module according to the target delay time signal, the transmitting time signal and the receiving time signal. The receiving module receives the corresponding delay time signal and delays the transmission of the package according to the delay time signal such that the data link layer receives each package at the same time.