Serial Bit-Stream Transmitter ISI Mitigation via Clock Phase Adjustment
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Solution Overview
Problem
Existing data transmission systems face issues with inter-symbol-interference (ISI) leading to increased bit error ratios due to jitter, which current solutions attempt to address by increasing voltage amplitude, resulting in higher power consumption and potential additional jitter.
Innovation Solution
The method involves buffering and detecting predefined bit sequences prone to ISI, adjusting the clock phase to prolong the transmission duration of specific bits, thereby alleviating ISI without increasing power consumption or introducing additional jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage amplitude is increased to compensate for inter-symbol-interference, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent changes the time parameter (bit duration) instead of the voltage parameter to compensate for ISI. By detecting predefined bit sequences susceptible to ISI and adjusting the clock phase, the system prolongs the transmission duration of affected bits, allowing them to reach their voltage levels despite channel attenuation and delay, thereby maintaining signal quality without increasing power consumption.
2Reliability
If voltage amplitude is increased to compensate for inter-symbol-interference, then signal quality is improved, but additional jitter may occur
Solution Approach 1:
The patent uses time-domain parameter adjustment (bit duration) rather than voltage amplitude adjustment. By extending the transmission time of bits affected by ISI through clock phase adjustment, the system allows these bits to reach their target voltage levels without the harmful effects of over-compensation that would cause additional jitter.
3Reliability
If transmission duration of specific bits is prolonged to compensate for ISI, then inter-symbol-interference is reduced, but transmission time increases
Solution Approach 1:
The system performs preliminary detection of bit sequences susceptible to ISI before transmission. By identifying predefined patterns that are prone to inter-symbol-interference in advance, the system can proactively adjust the clock phase and prolong transmission duration only for those specific bits, rather than uniformly extending all bit durations.
Solution Approach 2:
The patent applies differential treatment to different bits based on their susceptibility to ISI. Instead of uniformly prolonging all bit transmission durations, the system selectively extends the transmission time only for bits belonging to detected predefined sequences that are prone to inter-symbol-interference, thereby minimizing the overall impact on transmission time while effectively compensating for ISI where needed.
4Reliability
If four different voltage levels are provided to compensate for ISI, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent avoids increasing the voltage level parameter by instead changing the time parameter. The system maintains the conventional two-level voltage scheme but compensates for ISI by adjusting the duration of bit transmission through clock phase manipulation, thereby achieving signal quality improvement without the complexity of implementing four different voltage levels.
Data Source
AI summary
The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.