Serial Transmitter Duty-Cycle Correction for Deterministic Jitter
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Solution Overview
Problem
High-speed serial data transmitters face significant deterministic jitter due to clock duty-cycle distortion, particularly in low-power systems where small I/O driver circuits make calibration challenging to meet duty-cycle distortion specifications.
Innovation Solution
A circuit comprising a serial data transmitter, a pattern generator, and a duty cycle detection and correction circuit, which includes a capacitor, switched charge pump, and clocked comparator to measure and correct duty cycle errors by generating an adjusted clock signal, using a finite state machine to control the pattern generator and multiplexer to transmit specific bit patterns and calculate correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If small I/O driver circuits are used to reduce power consumption, then power consumption is reduced, but duty-cycle distortion increases making calibration difficult
Solution Approach 1:
The patent applies preliminary action by performing duty-cycle calibration before normal data transmission. The system uses a calibration mode where a known test pattern is transmitted and the duty-cycle error is measured and corrected in advance, ensuring that when normal operation begins, the duty-cycle distortion is already minimized. This allows small I/O driver circuits to be used without suffering from excessive duty-cycle distortion during actual data transmission.
Solution Approach 2:
The patent implements feedback by measuring the actual duty-cycle error of the clock signal and using this measurement to adjust and correct the duty-cycle distortion. The system includes a duty-cycle error measurement circuit that continuously monitors the clock signal and feeds this information back to a correction mechanism, creating a closed-loop system that automatically compensates for duty-cycle distortion caused by small I/O driver circuits.
2Manufacturing precision
If duty-cycle calibration is performed to meet specifications, then duty-cycle distortion is reduced, but system complexity and calibration time increase
Solution Approach 1:
The patent merges the duty-cycle calibration function with the normal data transmission path by using the same I/O driver circuits and signal paths for both calibration and operational modes. The calibration process reuses existing components such as the serializer, I/O drivers, and measurement circuits, rather than adding separate dedicated calibration hardware. This integration reduces overall system complexity while still achieving effective duty-cycle correction.
Solution Approach 2:
The patent applies universality by designing the calibration system to perform multiple functions: the same circuitry used for normal data transmission is also used for duty-cycle calibration and measurement. The I/O driver circuits, serializer, and measurement circuits serve dual purposes during calibration mode and normal operation mode, eliminating the need for separate dedicated calibration components and reducing overall system complexity.
3Speed
If double data rate clock is used to increase transmission speed, then data transmission speed is improved, but duty-cycle distortion has greater impact on deterministic jitter
Solution Approach 1:
The patent applies preliminary action by correcting the duty-cycle distortion of the double data rate clock before it is used for high-speed data transmission. The calibration process measures and corrects the clock duty-cycle error in advance, ensuring that the clock signal has minimal duty-cycle distortion before being used to drive the high-speed serial transmitter. This preliminary correction prevents deterministic jitter from degrading the high-speed transmission performance.
Solution Approach 2:
The patent implements feedback by continuously monitoring the duty-cycle error of the double data rate clock and using this information to adjust and correct the clock signal. The measurement circuit detects duty-cycle distortion in the clock and feeds this error signal back to a correction mechanism that adjusts the clock duty-cycle, thereby reducing deterministic jitter and improving the reliability of high-speed data transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces duty-cycle distortion in serial data transmitters, improving performance by accurately measuring and correcting clock duty cycle errors, thereby enhancing the reliability of high-speed data transmission.
Implementation Method 1
a switched charge pump, configured: to charge the capacitor when the output of the serial data transmitter is in a first state and to discharge the capacitor when the output of the serial data transmitter is in a second state
Implementation Method 2
a clocked comparator, configured to compare a voltage on the capacitor and a reference voltage, at a sampling time defined by a transition in a clock signal
Data Source
AI summary
A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.