Serial XOR Circuit With Parallel XNOR Outputs for Faster Parity
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Solution Overview
Problem
Existing XOR gate architectures for computing parity in error detection and correction schemes are slow due to the need for two-input XOR gates, which require internal or external complement signals, leading to inefficiencies in cascading and increased delay stages.
Innovation Solution
A serial XOR calculation circuit using a cascade of logic circuits, each producing both XOR and XNOR outputs, allowing for efficient computation of multiple input signals with reduced delay stages by sharing transistor resources and optimizing transistor sizes for increased speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two-input XOR gates are used for parity computation, then the circuit can be implemented with standard logic gates, but the computation speed is slow due to multiple delay stages
Solution Approach 1:
The patent segments the XOR computation into parallel paths: one path computes the XOR function while another path computes the complement signal in parallel. This segmentation allows both the XOR result and its complement to be available simultaneously, eliminating the sequential delay where the complement must wait for the XOR computation to complete first.
Solution Approach 2:
The patent performs preliminary computation of complement signals in parallel with the main XOR computation. By preparing the complement signals beforehand and in parallel rather than sequentially after the XOR operation, the circuit reduces the overall computation time and delay stages required for error correction operations.
2Adaptability or versatility
If complement signals are computed internally in XOR gates, then the gate functionality is complete, but the computation requires two delay stages reducing speed
Solution Approach 1:
The patent merges the XOR computation function with the complement signal generation into a single parallel operation. Instead of having separate sequential stages for computing XOR and then computing its complement, the circuit combines both functions to operate simultaneously, maintaining complete gate functionality while improving speed by eliminating the sequential dependency.
3Speed
If external computation of complement signals is used, then XOR gate may require only single delay stage, but external circuit suffers delay stage penalty
Solution Approach 1:
The patent introduces an intermediary parallel computation path that generates complement signals simultaneously with the XOR computation. This intermediary path acts as a mediator that provides the complement signals exactly when needed without adding external delay, effectively eliminating the bottleneck that would otherwise exist in externally-computed complement signal architectures.
4Adaptability or versatility
If XOR gates are cascaded in large numbers for n-input XOR, then the circuit can handle multiple inputs, but signal drive capability gets progressively weaker
Solution Approach 1:
The patent transitions from a single-dimensional serial cascading approach to a multi-dimensional parallel architecture. By computing XOR results and complement signals in parallel dimensions rather than sequentially cascading through multiple gates, the circuit maintains strong signal drive capability even when handling large numbers of inputs, as the parallel paths do not progressively degrade the signal strength.
Data Source
AI summary
In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided. The calculation circuit includes: a plurality of logic circuits arranged from a first logic circuit to a last logic circuit, wherein each logic circuit is configured to receive two logical input signals and the complement of the two logical input signals and to provide an XOR output signal and an XNOR output signal, wherein the XOR output signal represents the XOR of its two input signals and the XNOR output signal represents an exclusive-NOT-OR (XNOR) of its two input signals, and wherein the first logic circuit receives two of the N input signals as its logical input signals, a second logic circuit receives another one of the N input signals and an XOR output signal from the first logic circuit as its logical input signals, and so on such that the last logic circuit receives a remaining one of the N input signals and an XOR output signal from a next-to-last logic circuit as its logical input signals.