Serialized Differential I/O with Forwarded Clock for Low-Latency Links
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Solution Overview
Problem
Conventional high-speed I/O data circuits face inefficiencies in transferring large volumes of data across short distances due to inadequate design specifications, high memory requirements, latency penalties, and improper digital design methods, leading to trade-offs between manufacturing cost and data communication speed.
Innovation Solution
A high-speed I/O data system utilizing differential serializing transmitters with multi-phase clock generators and pulse-controlled push-pull output drivers, which serialize NRZ data signals and clock signals, reducing power consumption and latency while maintaining high-speed data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional I/O interfaces are used, then design flexibility is maintained, but data transfer speed is insufficient for high-speed applications
Solution Approach 1:
The patent segments the data transfer interface into multiple specialized components: a serializer for parallel-to-serial conversion, a dedicated clock distribution network with multi-phase clock signals, and separate transmit/receive channels. This segmentation allows each component to be optimized for high-speed operation while maintaining overall system flexibility through modular architecture.
2Productivity
If packet-based communication is implemented, then data transfer capability is improved, but memory requirements and latency increase
Solution Approach 1:
The patent implements continuous data streaming through serialized parallel data streams, eliminating the start-stop nature of packet-based communication. The serializer continuously converts parallel data to serial format, and the differential signaling maintains continuous transmission, removing packet assembly/disassembly delays and reducing latency while preserving high data transfer capability.
3Speed
If full-custom I/O solutions are implemented, then data communication speed is improved, but power supply noise and signal integrity issues worsen
Solution Approach 1:
The patent introduces several intermediary elements to isolate and protect against noise: controlled-impedance transmission lines act as intermediaries between the serializer and receiver to maintain signal integrity; differential signaling serves as an intermediary that rejects common-mode noise; and dedicated clock distribution networks with buffer stages mediate between clock sources and data paths to prevent power supply noise coupling.
4Productivity
If data is transmitted in parallel form, then data volume transfer is efficient, but signal integrity and timing control deteriorate at high speeds
Solution Approach 1:
The patent transforms the data transmission from the spatial dimension (parallel multiple signals) to the temporal dimension (serial sequential signals). The serializer converts parallel data streams into a serialized format transmitted over differential pairs, and the receiver deserializes and reconstructs the parallel data. This dimensional transformation maintains data volume efficiency while improving signal integrity and timing control through standardized differential signaling.
Data Source
AI summary
In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.