Serialized Data Output Circuit for Power Domain Skew Alignment

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Solution Overview

Problem

Semiconductor data output circuits face challenges in reconciling different power domains, leading to signal attenuation and skew misalignment issues when transferring data across varying voltage levels.

Innovation Solution

The implementation of a data output circuit with a power domain changing unit and level shifters to generate and shift clock signals and data, ensuring compatibility across different power domains, and the use of repeaters and output units to serially convert and drive data, thereby compensating for skew misalignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is transferred across different power domains using conventional circuits, then data transfer is enabled, but signal attenuation and skew misalignment occur

Engineering Contradiction:
Improvesignal integrityVSAvoidpower domain reconciliation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a level shifter as an intermediary component between different power domains. The level shifter converts voltage levels from a first power domain to a second power domain, enabling clean signal transfer without direct coupling between domains. This mediator approach resolves the technical contradiction by maintaining signal integrity while managing power domain complexity through dedicated voltage translation hardware.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple power domains are used in semiconductor memories, then functional versatility is improved, but power domain reconciliation becomes complex

Engineering Contradiction:
Improvepower domain compatibilityVSAvoidpower domain reconciliation
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the power domain architecture into distinct, isolated domains (first power domain and second power domain) with dedicated level shifters for each interface. This segmentation allows each power domain to operate independently with its own voltage characteristics, while the level shifters provide controlled interfaces between them. The segmentation approach enables functional versatility across multiple power domains while managing reconciliation complexity through modular, localized voltage translation.

Inventive Principle:
Principle #1Segmentation

3Productivity

If conventional data output circuits are used, then data output is achieved, but skew misalignment between data and clock signals occurs

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidskew alignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies equipotentiality by ensuring that data signals and clock signals both undergo identical voltage level translation through matching level shifters. By placing level shifters on both data and clock paths with matched characteristics, the patent creates equipotential conditions that preserve the temporal relationship between signals. This approach maintains skew alignment precision while enabling efficient data transfer across power domain boundaries.

Inventive Principle:
Principle #12Equipotentiality

Data Source

PatentUS8212694B2Data output circuit
Publication Date: 2012.07.03 SK HYNIX INC
  • US8212694B2 patent drawing
  • US8212694B2 patent drawing
  • US8212694B2 patent drawing

AI summary

A data output circuit is presented. The data output circuit includes: a data serializer and a driver. The data serializer is configured to generate serial data using first parallel data. The driver is configured to drive the serial data to generate output data. The data serializer is also configured to generate the serial data by multiplexing second parallel data generated by changing a power domain of the first parallel data.