Serialized Compressed Scan Control Signal Generation
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Solution Overview
Problem
The integration of a large number of transistors in a single chip increases the execution time and cost of scan tests, making it challenging to implement serialized compressed scan architectures (SCSA) with non-standard test interfaces in integrated circuits (ICs, as existing technologies face difficulties in directly integrating test interfaces compliant with standard test standards.
Innovation Solution
An integrated circuit device and method that generate input control signals for a serialized compressed scan circuit, including a clock input port, state enable bus, control signal generating device, and clock gating device, which produce shift enable, capture enable, and strobe signals to control the test clock signal as serialized scan and scan clock signals, facilitating efficient test integration across various interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of scan chains is increased to reduce test cost, then the scan chain length is decreased and testing time is reduced, but the test data volume increases requiring compression circuits
Solution Approach 1:
The test data is segmented into multiple compressed scan chains, allowing parallel testing while maintaining reduced data volume through compression circuits. The scan chains are divided into segments that can be independently compressed and tested.
Solution Approach 2:
Composite testing architecture combining multiple scan chains with compression circuits creates a hybrid system that achieves both reduced testing time and controlled data volume. The composite structure integrates parallel scan chains with data compression functionality.
2Productivity
If a serialized compressed scan architecture with non-standard test interface is implemented, then test efficiency is improved, but direct integration with standard test interfaces becomes difficult
Solution Approach 1:
A controller is introduced as an intermediary component that bridges the non-standard serialized compressed scan interface and standard test interfaces. The controller translates between different interface protocols, enabling compatibility while maintaining the efficiency benefits of the serialized compressed architecture.
Solution Approach 2:
The controller is designed with multi-functional capability to handle both standard and non-standard test interfaces, making the system adaptable to different testing scenarios. The universal controller can operate in multiple modes to support various interface standards.
3Device complexity
If more transistors are integrated in a single chip, then circuit functionality is enhanced, but the execution time and test cost of scan tests increase
Solution Approach 1:
The large chip circuit is segmented into multiple smaller scan chains, allowing parallel testing that reduces overall execution time. By dividing the complex circuit into manageable segments, the testing process can proceed simultaneously across multiple chains.
Solution Approach 2:
The scanning process uses periodic clock signals to systematically cycle through different scan chains in a coordinated manner. This periodic action enables efficient traversal of the entire circuit while maintaining organized test sequencing.
Data Source
AI summary
A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal. A clock gating device is coupled to the control signal generating device, and receives the shift enable signal, the capture enable signal and the strobe signal. When the shift enable signal is enabled, the clock gating device controls the test clock signal as a serialized scan clock signal. When the strobe signal or the capture enable signal is enabled, the clock gating device controls the test clock signal as a scan clock signal.