4:1 Serializer Output Stage With Active Inductor Bandwidth Extension
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Solution Overview
Problem
Designing a time-interleaved 4-way data serializing digital-to-analog converter (DAC) with quarter-rate clocking poses a challenge in achieving high bandwidth at the output while maintaining static and dynamic linearity, especially at data-rates exceeding 112 Gb/s, as conventional passive inductor solutions require impractically small and high-quality inductors to effectively cancel out parasitic capacitance.
Innovation Solution
The implementation of an active inductor-based bandwidth extension technique using a gate-resistor-peaked n-type transistor load as an active inductor in a two-stage output stage, coupled with a current steering switch and shunt peaking inductor, enables high-bandwidth quarter-rate 4-way data serialization, effectively compensating for parasitic capacitance and extending the output bandwidth of the 4:1 serializer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If passive inductors are used to cancel parasitic capacitance and extend bandwidth, then bandwidth extension is achieved, but the inductors required are impractically small and have high quality requirements making them difficult to manufacture
Solution Approach 1:
The patent replaces passive mechanical inductors with an active inductor implemented using a transistor circuit (specifically a common-source amplifier configuration with a transistor and drain resistor). This substitution eliminates the need for physically small, high-Q passive inductors while achieving the same bandwidth extension function through active circuitry that can be fabricated using standard CMOS processes.
Solution Approach 2:
The patent changes the fundamental parameter of inductor implementation from passive physical components to active electronic components. By using a transistor-based active inductor, the design transforms the bandwidth extension mechanism from relying on physical inductor properties (size, Q-factor) to relying on circuit parameters (transistor gain, resistance values) that are easier to control and manufacture.
2Use of energy by moving object
If quarter-rate clocking architecture is used to reduce power consumption, then power efficiency is improved, but achieving high bandwidth at the DAC output becomes more challenging
Solution Approach 1:
The patent introduces an active inductor as an intermediary element between the DAC output and the transmission line. This active inductor acts as a bandwidth extension circuit that compensates for the limited bandwidth caused by quarter-rate clocking, allowing the system to maintain both low power consumption and high output bandwidth by mediating the signal transmission.
Solution Approach 2:
The patent changes the operating parameters of the output stage by implementing an active inductor that extends the usable bandwidth beyond what would be expected from quarter-rate clocking alone. This allows the system to operate at lower clock rates (reducing power) while still achieving high effective bandwidth through the bandwidth extension provided by the active inductor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the transmission of 112 Gbaud data with minimal amplitude and phase distortion, achieving high linearity performance and reducing power consumption, making it suitable for mega-data centers, 5G base stations, and supercomputers without the need for passive inductors, which are physically impractical.
Implementation Method 1
an active inductor-based bandwidth extension technique using a gate-resistor-peaked n-type transistor load as an active inductor
Implementation Method 2
effectively compensating for parasitic capacitance and extending the output bandwidth
Implementation Method 3
coupled with a current steering switch and shunt peaking inductor, enables high-bandwidth quarter-rate 4-way data serialization, effectively compensating for parasitic capacitance and extending the output bandwidth
Data Source
AI summary
An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.