Serializer Clock Emphasis for Wider Data Eye at High Speed
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Solution Overview
Problem
Current semiconductor systems face challenges in high-speed operation with low power consumption, as serializers struggle to precisely convert data in synchronization with modern clock speeds, leading to decreased data eye and valid window due to inter-symbol interference.
Innovation Solution
A transmitting circuit is introduced, comprising a clock generation circuit and serializer, which performs an emphasis operation on clock signals based on data to generate output clock signals, thereby synchronizing data output and extending the data eye and valid window by adjusting clock pulse widths and phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of the system is increased and clock speed is increased, then data processing speed is improved, but data eye and valid window decrease due to inter-symbol interference
Solution Approach 1:
The patent applies preliminary action by performing an emphasis operation on clock signals before data output. The clock generation circuit generates output clock signals with adjusted pulse widths and phases based on previous data values, preparing the clock timing in advance to prevent inter-symbol interference and maintain data eye even at high speeds
Solution Approach 2:
The patent changes the parameters of clock signals dynamically. The clock generation circuit adjusts the pulse width and phase of output clock signals based on the values of previous data, creating different clock timing characteristics for different data patterns to eliminate inter-symbol interference and maintain reliable data transmission
2Use of energy by moving object
If the system is designed for low power consumption with decreased amplitudes, then power consumption is reduced, but data transmission precision deteriorates
Solution Approach 1:
The patent changes the timing parameters of clock signals rather than increasing amplitude. By adjusting pulse width and phase of clock signals based on data patterns, the system maintains precise data transmission at low amplitudes, achieving both low power consumption and high precision without needing to increase signal strength
Data Source
AI summary
A transmitting circuit may include a clock generation circuit and a serializer. The clock generation circuit may generate a plurality of output clock signals by performing an emphasis operation for a plurality of clock signals based on a plurality of data. The serializer may output the plurality of data as output data in synchronization with the plurality of output clock signals.