Serializer Clock-Phase Output Scheme to Reduce Skew and Jitter
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Solution Overview
Problem
High-speed semiconductor systems face challenges in reducing data output time and improving signal integrity due to the need for converting internal clock signals into pulse width signals, which introduces phase skew and jitter.
Innovation Solution
A serializer design that samples data using internal clock signals without converting them into pulse width signals, utilizing data selectors with specific circuit configurations to output data in sequence while maintaining a high impedance state during disable periods, thereby reducing transmission path and eliminating phase skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If internal clock signals are converted into pulse width signals corresponding to unit period of output data, then data output timing can be controlled, but phase skew and jitter are introduced degrading signal integrity
Solution Approach 1:
The patent extracts and eliminates the clock signal conversion stage from the data transmission path. By directly using the internal clock signal to control the data selection and output process without converting it to pulse width signals, the invention removes the source of phase skew and jitter while maintaining precise data output timing control through the clock signal's natural phases.
2Measurement precision
If clock signal conversion is performed to control data output, then data transmission timing is regulated, but transmission time is increased due to additional conversion steps
Solution Approach 1:
The patent implements preliminary action by pre-organizing the data paths and selection logic to be directly controlled by the internal clock signal phases. The data selection and output control are prepared in advance with clear phase assignments, eliminating the need for real-time clock conversion and reducing data output time while maintaining precise timing control.
3Reliability
If data selectors use complex circuit configurations to sample data with internal clock signals, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent segments the data transmission function into multiple parallel data selectors, each handling specific data bits and controlled by specific clock phases. This segmentation allows each selector to use a relatively simple circuit configuration while collectively achieving high signal integrity through the coordinated operation of multiple selectors with dedicated clock phase control.
Data Source
AI summary
A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.