Serializer Clock Skew Reduction Using Multi-Frequency Synchronization
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Solution Overview
Problem
High speed data serializing apparatuses face issues with clock skew and glitches due to multiple clocks used in existing 2:1 serializers, leading to invalid data output and difficulties in high speed data transmission.
Innovation Solution
A serializer design that synchronizes data with multiple clocks of different frequencies using a combination of synchronization units, D flip-flops, and shift registers, including a divider, inverter, and multiplexers to minimize clock skew and glitches, allowing for high speed serializing operations without errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple 2:1 serializers are used to achieve high speed serializing, then the serializing speed is improved, but clock skew occurs between the multiple clocks
Solution Approach 1:
The patent merges multiple clock synchronization functions into a single unified serializer structure. Instead of using separate 2:1 serializers with independent clocks that cause skew, the invention combines parallel data inputs and synchronizes them with a single clock signal through integrated D flip-flops and multiplexers, eliminating inter-clock skew while maintaining high serializing speed.
Solution Approach 2:
The serializer is designed with multi-functional components that handle both data serialization and clock synchronization within a single device. The D flip-flops serve dual purposes of data latching and clock synchronization, while the multiplexer handles both data selection and timing alignment, reducing the need for multiple separate clocked devices that would introduce skew.
2Device complexity
If shift registers are used for serializing data, then the data transmission is simplified, but clock loading effects occur
Solution Approach 1:
The patent segments the serialization function across multiple parallel D flip-flops rather than using a single shift register chain. Each flip-flop handles a portion of the parallel data independently, distributing the clock loading across multiple lightweight stages rather than one heavy shift register, thereby reducing overall clock loading effects while maintaining structural simplicity.
3Productivity
If high speed clock is used to convert parallel data to serial data, then the serializing speed is improved, but glitches and invalid data output occur
Solution Approach 1:
The patent applies preliminary synchronization action by using D flip-flops to latch and synchronize all parallel data inputs with the high-speed clock before serialization. This preliminary timing alignment ensures that all data is stable and properly synchronized at the clock edges, preventing glitches and invalid data output during the high-speed serialization process.
Data Source
AI summary
Provided are a serializer that synchronizes data with a clock by using an inversion clock and a high speed serializing apparatus using both a serializer and a serializer including shift registers. Such a serializer may include a first synchronization unit suitable for synchronizing input data with a first synchronization clock, a multiplexer suitable for serializing output data of the first synchronization unit based on the first synchronization clock, and a second synchronization unit suitable for synchronizing output data of the multiplexer with a second synchronization clock which is different from the first synchronization clock in frequency.