Serializer Clock Switching for Jitter-Tolerant Receiver Connectivity
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Solution Overview
Problem
Conventional transmitter apparatuses have limited connectivity with various receiver apparatuses due to mismatched clock transmission schemes and high jitter levels in serial data transmission, leading to noise and failure in recovering parallel data signals.
Innovation Solution
A semiconductor integrated circuit that dynamically adjusts clock transmission schemes and jitter removal based on receiver characteristics, using a clock generation circuit, frequency divider, selector, and control circuit to optimize clock signal transmission, allowing switching between coherent and non-coherent clocking schemes and varying transmission characteristics to match receiver apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed clock transmission scheme is used, then the transmitter apparatus can be simple in structure, but the connectivity with various receiver apparatuses is limited
Solution Approach 1:
The transmitter apparatus dynamically switches between coherent and non-coherent clock transmission schemes based on the receiver apparatus type. A selector circuit chooses between different clock signals (divided clock for coherent, reference clock for non-coherent) according to receiver characteristics, enabling adaptability without permanent complex structure for all modes
Solution Approach 2:
The clock generation circuit serves multiple functions: it generates the reference clock for parallel-serial conversion, produces the divided clock signal for coherent transmission, and outputs the reference clock for non-coherent transmission. This multi-functionality reduces the need for separate dedicated circuits for each transmission mode
2Speed
If high frequency serial data transmission is used, then data transmission speed is improved, but jitter increases causing noise and recovery failure
Solution Approach 1:
The transmitter apparatus provides feedback information about the clock transmission scheme to the receiver apparatus. The receiver uses this information to select the appropriate clock recovery method, ensuring reliable parallel data signal recovery by matching the recovery process to the transmitted signal characteristics
Solution Approach 2:
The system changes the clock signal parameters (frequency division ratio, phase relationship) based on the transmission mode. In coherent mode, the clock is divided by 10 from the 10-times clock; in non-coherent mode, the reference clock is transmitted directly. This parameter adaptation optimizes both transmission speed and recovery reliability
Data Source
AI summary
A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.