Serializer Clocking Architecture for Low-Power High-Speed Output
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Solution Overview
Problem
Conventional serializers using current mode logics and standard cells for high-speed data transmission experience high power consumption, larger chip area, and manufacturing costs, while also inducing data errors due to noise and corner variations between differential and full swing clocks.
Innovation Solution
A serializer design incorporating parallel-input-serial-output (PISO) shift registers, current-mode-logic (CML) D flip-flops, and a multiplexer that operates using a full swing clock and a noiseless differential clock, ensuring synchronous operation and minimizing data errors and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current mode logics are used in serializer for high speed data transmission, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The serializer is divided into two distinct parts: standard cell components (PISO shift registers) for data serialization and CML components (D flip-flops, multiplexers) for data latching and selection. This segmentation allows each part to operate in its optimal mode, with standard cells handling the bulk data transmission at lower power and CML components providing high-speed operation only where necessary for clocked operations.
2Speed
If current mode logics are used in serializer for high speed data transmission, then data transmission speed is improved, but chip area increases
Solution Approach 1:
The serializer architecture segments functionality between standard cell implementations (PISO shift registers) and CML implementations (D flip-flops and multiplexers). Since standard cells occupy less area than CML components, this segmentation reduces overall chip area while maintaining high-speed performance through strategic placement of CML components only where high-speed operation is critical.
3Adaptability or versatility
If differential clock is converted to full swing clock using differential-to-single circuit, then clock compatibility is improved, but noise and corner variation are induced
Solution Approach 1:
The harmful conversion process from differential-to-single clock is completely removed from the system. Instead of converting the differential clock to full swing clock, the invention uses the noiseless differential clock directly to drive both the PISO shift registers (through standard cell logic) and the CML D flip-flops, eliminating the source of noise and corner variations while maintaining clock compatibility through direct differential signaling.
4Adaptability or versatility
If standard cells and current mode logics are operated with different clocks, then operational flexibility is improved, but synchronous operation cannot be achieved
Solution Approach 1:
Both the standard cell PISO shift registers and CML D flip-flops are merged into a single clock domain by driving them with the same differential clock signal. This eliminates the synchronization problems that arise from using different clocks while maintaining operational flexibility, as the unified clocking approach ensures that all components operate in lockstep without requiring complex inter-clock synchronization mechanisms.
Data Source
AI summary
The invention provides a serializer. In one embodiment, the serializer converts parallel input data into serial output data according to a full swing clock and a noiseless differential clock, and comprises a plurality of parallel-input-serial-output (PISO) shift registers, a plurality of current-mode-logic (CML) D flip-flops, and at least one multiplexer. The PISO shift registers respectively selects a plurality of received input bits from the input bits of the parallel input data, and respectively serializes the received input bits according to the full swing clock to generate a plurality of first middle data signals. The CML D flip-flops respectively latches the first middle data signals to generate a plurality of second middle data signals. The at least one multiplexer receives the second middle data signals, and interleaves the second middle data signals according to the noiseless differential clock to generate the serial output data.