Serializer DAC Randomization for Unit Cell Mismatch Reduction
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Solution Overview
Problem
Existing digital-to-analog converter (DAC) circuits face challenges in improving the quality of analog signals due to mismatch between unit cells, particularly at high resolution and high speed.
Innovation Solution
A DAC circuit that employs a serializer circuit with pseudo random number generation and switch circuits to convert parallel digital codes into serial codes, applying different random numbers to improve code randomness and reduce mismatch between unit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional DAC circuit uses a current array with multiple unit cells for high resolution and high speed operation, then the conversion speed and resolution are improved, but mismatch between unit cells degrades the quality of analog signals
Solution Approach 1:
The patent applies dynamic element matching (DEM) technique that dynamically switches between different unit cells using pseudo-random sequences. Instead of statically assigning fixed positions to unit cells, the circuit dynamically changes the mapping between digital codes and unit cells based on generated random sequences, thereby reducing the impact of mismatch errors while maintaining high conversion speed and resolution
Solution Approach 2:
The patent changes the parameter of code assignment by applying pseudo-random sequences to the digital codes before they are converted to analog signals. This parameter transformation randomizes the distribution of codes across unit cells, reducing systematic mismatch errors and improving signal quality without sacrificing conversion performance
2Reliability
If random numbers are applied to improve code randomness and reduce unit cell mismatch, then signal quality is improved, but circuit complexity increases due to additional pseudo random number generation and switch circuits
Solution Approach 1:
The patent segments the code generation process into multiple stages: original code generation, pseudo-random sequence generation, and combined code output. By dividing the functionality into separate modules (pseudo random number generation circuit, switch circuits, and code combination logic), the system achieves dynamic element matching while maintaining modular architecture that simplifies implementation and debugging
Solution Approach 2:
The patent introduces pseudo-random sequences as an intermediary element between the digital input codes and the unit cell selection. This intermediary randomization layer decouples the direct mapping relationship, allowing the system to reduce mismatch errors without fundamentally redesigning the core DAC architecture, thus managing complexity effectively
Data Source
AI summary
A digital-to-analog converter (DAC) circuit is provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo random number generation circuit configured to generate random numbers in response to edges of a first clock signal; a first switch circuit connected to a first multiplexer; a second switch circuit connected to a second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo random number generation circuit in response to different edges of the first clock signal to the first switch circuit and the second switch circuit, respectively.