Serializer Deserializer Bus Interface I/O Pin Reduction
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Solution Overview
Problem
The complexity and cost of System-on-a-Chip (SoC) designs increase exponentially due to the high number of communication lines required for AMBA bus interfaces, exceeding the limit of available I/O pins, making it impractical for systems with multiple masters and slaves.
Innovation Solution
The implementation of serializers and deserializers in the bus system reduces the number of communication lines needed by serializing parallel bus information, allowing for efficient communication between chips using a smaller number of lines, thereby reducing the complexity and cost of the SoC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard AMBA AHB and APB bus interfaces are used to connect multiple masters and slaves across chips, then communication capability is improved, but the number of I/O pins required increases exponentially
Solution Approach 1:
The patent transforms the parallel bus interface into a serial communication interface, changing the dimension of data transmission from wide parallel buses to narrow serial streams. This dimensional change allows the same communication capability to be achieved with far fewer physical pins, as serial communication multiplexes multiple data lines into a single or few time-multiplexed channels.
Solution Approach 2:
The patent changes the key parameter of communication from parallel width to serial rate. By increasing the serial communication rate and using efficient serialization/deserialization protocols, the system maintains the required data throughput while dramatically reducing the number of physical connection lines needed between chips.
2Adaptability or versatility
If the number of AHB and APB interface buses is increased to support more masters and slaves, then system functionality is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal serial interface that can handle multiple masters and slaves through a single communication channel. The serial interface uses protocol-level multiplexing to distinguish between different masters and slaves, replacing the need for dedicated parallel buses for each device combination. This universal interface reduces system complexity while maintaining full functionality.
Solution Approach 2:
The patent introduces serialization and deserialization logic as intermediary components that translate between the parallel internal bus interface and the serial external communication interface. These intermediaries abstract the complexity of multi-device communication, allowing the system to support multiple masters and slaves through a standardized serial protocol rather than requiring complex direct parallel connections between all device pairs.
3Speed
If parallel bus information is transmitted directly between chips, then communication speed is maintained, but the number of communication lines becomes impractically large
Solution Approach 1:
The patent resolves this contradiction by changing from spatial parallelism (multiple simultaneous lines) to temporal parallelism (time-multiplexed serial lines). The serial interface transmits multiple data bits sequentially in time, achieving the same information throughput through a single or few lines by utilizing the time dimension rather than requiring multiple spatial lines.
Solution Approach 2:
The patent employs periodic clocking and time-multiplexed transmission in the serial interface. Data is transmitted in periodic clock cycles with structured frames that carry multiple pieces of information sequentially. This periodic serial transmission achieves efficient data transfer rates while using minimal physical lines, replacing the need for large numbers of simultaneous parallel lines.
Data Source
AI summary
Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a slave in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from a bus matrix to the shift registers for serialization and communication to the slave, where the mechanism provides deserialized information received from the shift registers to a bus matrix. The mechanism inserts one or more wait cycles in communication with the matrix during the serialization and deserialization.