Serializer Driver Current Adjustment for Low-Jitter High-Speed Signals

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Solution Overview

Problem

High-speed signal paths face delays and jitter issues due to reduced current supply capability of drivers, which hinder full oscillation of signal outputs.

Innovation Solution

The implementation of a circuit with adjustment circuits using P-channel and N-channel MOS transistors, connected in parallel, that adjust current supply capabilities based on code signals to ensure full oscillation and minimize jitter, even at minimum current supply levels, by using de-emphasis circuits and resistor networks to maintain signal amplitude.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the current supply capability of a driver is lowered to adjust signal timing, then signal delay is reduced, but the signal output cannot fully oscillate leading to jitter

Engineering Contradiction:
Improvesignal delayVSAvoidsignal oscillation stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The driver circuit is segmented into multiple parallel current paths with different current supply capabilities. Each path can be independently controlled to provide the necessary current for full oscillation while adjusting the overall timing characteristics of the signal output.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the current supply parameter by providing multiple current levels through parallel paths. This allows the system to maintain full oscillation by selecting appropriate current levels while still achieving timing adjustment through controlled current selection.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the current supply capability of a driver is adjusted to manage signal timing, then timing control is improved, but signal amplitude decreases preventing full oscillation

Engineering Contradiction:
Improvetiming controlVSAvoidsignal amplitude
Core Design Contradiction:
Ease of operationVSPower

Solution Approach 1:

The driver circuit dynamically selects from multiple current supply paths based on timing requirements. This dynamic configuration allows the system to adjust timing control while maintaining sufficient current amplitude for full signal oscillation through real-time path selection.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The parallel current paths serve multiple functions: they provide timing adjustment capability while simultaneously ensuring sufficient current amplitude for full oscillation. This multi-functionality resolves the contradiction between timing control and signal power.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for precise adjustment of signal timing and amplitude, preventing jitter and ensuring full oscillation across varying current supply conditions, effectively managing signal delays in high-speed signal paths.

Implementation Method 1

adjustment circuits using P-channel and N-channel MOS transistors, connected in parallel, that adjust current supply capabilities based on code signals

Methodology Applied
Scientific EffectField Effect Transistor operation: Conduction (electrical)

Data Source

PatentUS11552626B2High speed signal adjustment circuit
Publication Date: 2023.01.10 MICRON TECHNOLOGY INC
  • US11552626B2 patent drawing
  • US11552626B2 patent drawing
  • US11552626B2 patent drawing

AI summary

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.