Serializer Latency Buffer with Adaptive Time Shift Alignment
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Solution Overview
Problem
Existing serializer circuits require large memory space and complex control logic to achieve temporal alignment of parallel data streams, leading to increased circuit area and power consumption.
Innovation Solution
A serializer circuit with a multiplexer, FIFO circuit, and timing control circuit that adjusts the master clock signal and select signal sequence in response to temporal shift signals, allowing for temporal alignment with reduced memory and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large parallel in/serial out FIFO circuit is used to store multiple data words for temporal re-alignment, then temporal alignment capability is improved, but circuit area and power consumption increase significantly
Solution Approach 1:
The patent divides the temporal alignment function into two separate components: a small FIFO circuit for basic buffering and a latency buffer circuit for precise temporal adjustment. This segmentation allows each component to be optimized independently, reducing the overall circuit area while maintaining temporal alignment capability.
Solution Approach 2:
The latency buffer circuit acts as an intermediary between the small FIFO and the serializer, providing precise temporal adjustment without requiring the large FIFO to handle all alignment requirements. This intermediary approach enables the system to achieve temporal alignment with much smaller memory resources.
2Adaptability or versatility
If a large parallel in/serial out FIFO circuit with address control and pointer circuitry is used, then temporal re-alignment flexibility is improved, but device complexity increases
Solution Approach 1:
The patent extracts the complex address control and pointer circuitry from the FIFO design and relocates the temporal alignment function to a separate latency buffer circuit. This extraction simplifies the FIFO to basic buffering operations while maintaining re-alignment flexibility through the dedicated latency buffer with its own simplified control logic.
Solution Approach 2:
The latency buffer circuit uses dynamic control signals (LATENCY_BUFFER_LOAD, LATENCY_BUFFER_CLK_EN, LATENCY_BUFFER_RD_PTR) to adaptively adjust temporal alignment in real-time. This dynamic approach provides re-alignment flexibility without requiring complex static control logic, allowing the system to respond flexibly to timing requirements.
3Reliability
If multiple data words from past inputs are stored to accommodate maximal latency, then temporal alignment range is improved, but power consumption increases
Solution Approach 1:
The patent segments the temporal alignment function between a small FIFO and a latency buffer circuit, where only the latency buffer stores multiple data words for maximal latency accommodation. This segmentation concentrates the power-intensive storage operation in a dedicated circuit with optimized control, reducing overall power consumption compared to a large FIFO handling all storage requirements.
Solution Approach 2:
The latency buffer circuit uses dynamic clock enabling (LATENCY_BUFFER_CLK_EN) and load control (LATENCY_BUFFER_LOAD) to power down or minimize operation when full buffering capacity is not needed. This dynamic power management allows the circuit to maintain the capability for wide temporal alignment range while consuming power only when required, significantly reducing average power consumption.
Data Source
AI summary
Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.