Multi-Stage Serializer for Odd Gearing Ratios
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Solution Overview
Problem
Traditional serializers for programmable logic devices, such as FPGAs, face inefficiencies and high silicon and power costs when achieving odd gearing ratios, particularly for 7:1 gearing ratios, due to the need for additional rate-conversion logic.
Innovation Solution
A serializer design that dynamically configures to operate as an N:1 serializer, using a combination of transfer, update, and serializing stages with flip-flops and multiplexers, employing DDR sampling and a dual clock system to efficiently support odd gearing ratios without the need for extra rate-conversion logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional rate-conversion logic is used to achieve odd gearing ratios (e.g., 7:1), then the desired gearing ratio is achieved, but silicon cost and power consumption increase significantly
Solution Approach 1:
The serializer is designed with a universal architecture that can achieve multiple gearing ratios (including odd ratios like 7:1) without requiring separate rate-conversion logic for each ratio. The same core serialization circuitry handles different gearing ratios by adjusting operational parameters, eliminating the need for additional dedicated hardware for each ratio configuration.
Solution Approach 2:
The invention changes operational parameters (such as clock phase relationships and data sampling timing) to achieve different gearing ratios using the same hardware structure. By varying these parameters, the serializer can adapt to odd gearing ratios like 7:1 without adding extra rate-conversion logic, thus reducing silicon cost while maintaining versatility.
2Adaptability or versatility
If traditional rate-conversion logic is used to achieve odd gearing ratios (e.g., 7:1), then the desired gearing ratio is achieved, but power consumption increases significantly
Solution Approach 1:
The serializer uses a universal design that performs multiple gearing ratio functions through a single circuit implementation. This eliminates the need for separate rate-conversion logic blocks that would each consume power, thereby reducing overall power consumption while maintaining the ability to achieve odd gearing ratios like 7:1.
Solution Approach 2:
The invention achieves different gearing ratios by changing operational parameters rather than activating additional logic circuits. This parameter-based approach keeps the same hardware components operating at different settings, avoiding the power overhead of enabling and operating separate rate-conversion logic for each ratio.
3Device complexity
If SDR sampling is used with sampling clock at the same rate as high-speed serial data stream, then simple clocking is achieved, but clock skew tolerance is limited
Solution Approach 1:
The invention employs periodic action through dual-edge triggered flip-flops that sample data on both rising and falling edges of the sampling clock. This periodic sampling approach effectively doubles the sampling frequency without requiring a faster clock, thereby increasing clock skew tolerance while keeping the clocking structure relatively simple and avoiding the need for completely complex clocking schemes.
Data Source
AI summary
In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N−1 operating mode and an N+1 operating mode.