Serializer Clock Phase Reset for Early Bit Error Reduction
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Solution Overview
Problem
Serializer devices face challenges in maintaining an appropriate phase difference between the first clock and the load signal, leading to bit errors when there is no bidirectional communication or slow communication lines, resulting in prolonged high bit error rates.
Innovation Solution
Incorporating a phase difference detection unit and a reset instruction unit to detect and adjust the phase difference between the third clock and the first clock, and between the load signal and the first clock, allowing for immediate correction of phase differences within target ranges, even in the absence of fast bidirectional communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bidirectional communication is implemented for error notification, then the serializer device can restore phase difference to appropriate range, but the system complexity and communication requirements increase
Solution Approach 1:
The serializer device performs self-diagnosis by detecting phase difference between clocks internally and autonomously resetting its own operation state without requiring external error notifications, thereby eliminating the need for complex bidirectional communication while maintaining reliability
Solution Approach 2:
The device implements internal feedback by continuously monitoring phase difference between the first clock and third clock, and automatically adjusting its operation state based on this feedback to maintain appropriate phase relationships without external intervention
2Reliability
If slow communication line is used for error notification, then the system configuration is simpler, but it takes longer time to restore phase difference and reduce bit error rate
Solution Approach 1:
The serializer device autonomously detects phase difference and resets its own operation state without waiting for external error notifications, eliminating communication delays and achieving immediate restoration of appropriate phase difference
Solution Approach 2:
The device continuously monitors phase difference in advance and performs preliminary reset actions before bit errors accumulate, preventing high bit error rate states rather than reacting to them after detection
3Reliability
If phase difference detection and reset functionality is added, then bit error rate is reduced more quickly, but the device complexity increases
Solution Approach 1:
The phase difference detection unit and reset control unit serve multiple functions: detecting phase relationships between clocks, determining operation state appropriateness, and controlling reset timing, thereby managing device complexity through multi-functional integration
Solution Approach 2:
The internal feedback mechanism continuously monitors phase difference and automatically adjusts operation state, creating a self-regulating system that improves reliability while keeping complexity manageable through automated control
Data Source
AI summary
A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instruction unit (17), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit (16) detects a phase difference between a first clock (CLK1) applied to the first latch unit (11) and a third clock (CLK3) applied to the second latch unit (12). The reset instruction unit (17) outputs a reset instruction signal (RSTn) to the frequency division unit (14) when the phase difference is not within a target range.