Multi-Lane Serializer Reset Synchronization for Low Inter-Pair Skew
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Solution Overview
Problem
In multi-lane serializer devices, the input timings of the first clock to respective serializer circuits can be slightly different due to lane skew, leading to significant differences in output timing of serial data between serializer circuits, which may not satisfy Inter Pair Skew (IPS) specifications, and existing solutions to reduce bit error rates are inefficient due to increased power consumption and layout area when using FIFOs.
Innovation Solution
A multi-lane serializer device with a controller that coordinates batch reset instructions to serializer circuits, including phase difference detectors and reset signal generators, to synchronize the phase difference between the load signal and the first clock across all serializer circuits, reducing bit error rates and IPS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual reset operations are performed in each serializer circuit to reduce bit error rate, then bit error rate is reduced, but Inter Pair Skew (IPS) increases due to lane skew causing different output timings
Solution Approach 1:
The patent merges the reset operations of multiple serializer circuits by introducing a master serializer that generates a unified reset signal. This reset signal is distributed to all serializer circuits simultaneously, ensuring they all reset at the same time despite lane skew, thereby reducing IPS while maintaining bit error rate reduction
Solution Approach 2:
The master serializer acts as an intermediary between the individual serializer circuits and the control system. It receives reset commands and distributes them synchronously to all serializer circuits, mediating the timing coordination to prevent IPS violations while enabling error correction
2Manufacturing precision
If FIFO memory is used to compensate for IPS between serializer circuits, then IPS specification is satisfied, but power consumption and layout area increase
Solution Approach 1:
The patent extracts the timing coordination function from the data path by implementing a separate control mechanism (master serializer with reset signaling). This eliminates the need for FIFO memory in the data path, reducing power consumption and layout area while maintaining IPS compliance through synchronous reset operations
3Device complexity
If communication line from receiver to transmitter is slow or non-existent, then system simplicity is maintained, but phase difference recovery time increases
Solution Approach 1:
The serializer circuits perform self-diagnosis by monitoring their own phase differences between the load signal and first clock. When an abnormality is detected, they autonomously initiate reset operations without requiring external notification, enabling rapid phase difference recovery while maintaining system simplicity
Data Source
AI summary
A multi-lane serializer device 1 includes serializer circuits 101 to 10N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.