Serializer Retiming Circuit for Phase-Aligned Data Multiplexing
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Solution Overview
Problem
Data serializers face challenges in efficiently converting parallel data signals to serial data signals while maintaining phase alignment and frequency compatibility, particularly in environments where parallel data buses operate at lower frequencies and need to be serialized at higher frequencies.
Innovation Solution
The proposed solution involves a serializer circuit comprising a recovery circuit, an adjusting circuit, and a multiplexer circuit, which generates a retimed data signal phase-aligned with a clock signal, and a second clock signal with a frequency twice that of the original, allowing for efficient serialization of multiple parallel data signals by aligning phases and frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel data signals are serialized directly without phase alignment, then serialization speed increases, but phase alignment and frequency compatibility deteriorate
Solution Approach 1:
The patent applies preliminary action by performing phase alignment and frequency matching of parallel data signals before serialization. The circuit retrieves original clock signals, aligns phases of multiple parallel data signals to these clock signals, and ensures frequency compatibility before the actual serialization process, thereby resolving the contradiction between speed and precision.
2Stability of the object's composition
If parallel data signals operate at lower frequencies, then signal stability improves, but data transmission efficiency deteriorates
Solution Approach 1:
The patent applies parameter changes by transforming the frequency parameter of parallel data signals during serialization. The circuit generates a serialized data signal at a higher frequency than the input parallel signals, thereby increasing data transmission efficiency while maintaining signal stability through proper phase alignment and clock recovery.
3Productivity
If multiple parallel data signals are serialized simultaneously, then throughput increases, but phase alignment complexity increases
Solution Approach 1:
The patent applies universality by using a single set of clock recovery and phase alignment circuitry to handle multiple parallel data signals. The circuit retrieves original clock signals that serve all parallel inputs and uses these unified clock references to align phases of multiple signals, thereby managing complexity while achieving high throughput serialization.
Data Source
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AI summary
A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.