Serializer Slew Rate Control Using Delayed Serial Data

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Solution Overview

Problem

Conventional slew rate controlling mechanisms for high-speed data communications, such as M-PHY, face challenges in controlling slew rates due to range and granularity limitations, especially in serializer/deserializer applications, where existing non-serializer/deserializer mechanisms are not applicable.

Innovation Solution

A serializer in an electronic device receives parallel data and clock rate information, converting it to serial data, and using a delay generator with components like a Phase Lock Loop, XOR gate, Low Pass Filter, and comparator to generate delays, which are then multiplexed with non-slew mode data to control slew rates, allowing for flexible slew rate configuration using RC devices or MOS transistors, and reducing the number of Field Effect Transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional slew rate controlling mechanisms are used, then the basic slew rate control function is achieved, but the control precision and flexibility are limited due to range and granularity limitations

Engineering Contradiction:
Improveslew rate control precisionVSAvoidcontrol mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the slew rate control into multiple discrete levels by dividing the control voltage range into different segments. Each segment corresponds to a specific slew rate range, allowing precise control through selective activation of different control voltage segments. This segmentation enables fine-grained adjustment of slew rates without requiring complex continuous control mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic slew rate control by making the control mechanism adaptable to different operating conditions. The system dynamically selects appropriate slew rate levels based on real-time requirements, transitioning between different control states as needed. This dynamic approach provides flexibility in adjusting slew rates while maintaining manageable device complexity through state-based control.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If non-serializer/deserializer slew control mechanisms are applied, then slew rate control is achieved for G1 mode, but the mechanism cannot be used for serializer/deserializer applications and other modes

Engineering Contradiction:
Improveslew control mechanism applicabilityVSAvoidimplementation difficulty
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent creates a universal slew rate control mechanism that functions across multiple application types including serializer/deserializer, non-serializer/deserializer, and various transmission modes (G1, G2-G5). The control mechanism uses a standardized approach with control voltage generation and multiplexer selection that can be applied uniformly across different applications, eliminating the need for separate control mechanisms for each application type while maintaining ease of implementation through consistent design patterns.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent achieves versatility by changing control parameters (control voltage levels and multiplexer selection) rather than changing the fundamental control mechanism structure. The same basic control architecture can serve different applications by adjusting voltage levels and selection signals, making the mechanism adaptable to serializer/deserializer, non-serializer/deserializer, and various gear modes without requiring separate implementations.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If additional capacitors and feed-forward transistors are added to control slew rate, then slew rate adjustment is possible, but the drive circuits are severely influenced by additional capacitive loads

Engineering Contradiction:
Improveslew rate adjustabilityVSAvoiddrive circuit performance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent introduces a control voltage as an intermediary element that mediates between the control logic and the output driver. Instead of directly modifying the driver circuit with capacitors and transistors, the control voltage acts as a mediator that adjusts the slew rate by controlling the charging/discharging rate of the output node. This intermediary approach provides slew rate adjustability while minimizing direct impact on drive circuit performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the mechanical approach of adding physical capacitors and transistors to the driver circuit with an electrical control approach using control voltages and multiplexers. Instead of mechanically modifying the driver structure, the system uses electrical signals to control the slew rate, substituting a less intrusive mechanism that maintains drive circuit reliability while achieving the desired adjustability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11881866B2Electronic device and method for controlling slew rate for high-speed data communications
Publication Date: 2024.01.23 SAMSUNG ELECTRONICS CO LTD
  • US11881866B2 patent drawing
  • US11881866B2 patent drawing
  • US11881866B2 patent drawing

AI summary

An electronic device and a method of controlling a slew rate for high-speed data communications are provided. The electronic device, according to an embodiment of the disclosure, includes a serializer configured to receive parallel data from another electronic device along with clock rate information, and convert the parallel data into serial data. The electronic device further includes a delay generator configured to generate a delay in the converted serial data using the clock rate information. The electronic device further includes a multiplexer configured to multiplex the converted serial data of the non-slew mode with the delayed data of the slew mode. The electronic device further includes a plurality of driver legs configured to receive the multiplexed data, and transfer the multiplexed data to the another electronic device. The electronic device further includes at least one of a voltage-controlled oscillator and a current-controlled oscillator configured to generate the clock rate information.