Multi-Lane Serializer Sync Loss Detection Using a Common Clock Divider
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed serial interface applications face synchronization loss issues due to Electro-static Discharge (ESD) events, leading to latency and inefficiencies in multi-lane transmitting apparatuses, as existing solutions either require complex clock signal distribution or are cost-inefficient with individual clock dividers in each lane.
Innovation Solution
A method and apparatus utilizing a Phase Locked Loop (PLL) circuit to generate a high-speed clock signal and sync reset signal, coupled with a common clock divider circuit to create a sync loss pulse, which is sampled by serializer circuits to detect synchronization loss, allowing for a logic block to reset the lanes and maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual clock dividers are used in each lane to detect synchronization loss, then detection accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the clock divider functionality into a single common clock divider circuit that serves all lanes, eliminating the need for individual clock dividers in each lane. This single clock divider generates a reference clock signal that is distributed to all serializer circuits, reducing device complexity and cost while maintaining synchronization loss detection capability through the shared reference signal.
Solution Approach 2:
The common clock divider circuit performs multiple functions: it generates the reference clock signal for all lanes, provides a timing reference for synchronization loss detection, and enables centralized control of the serialization process. This multi-functional design replaces what would otherwise require multiple dedicated clock divider circuits, one per lane.
2Reliability
If complex clock signal distribution is implemented to maintain synchronization, then synchronization reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines the clock distribution function into a single common clock divider that generates a unified reference clock signal distributed to all lanes. This eliminates the need for complex individual clock distribution networks, reducing device complexity while maintaining synchronization reliability through the shared reference signal that all serializers use for timing.
Solution Approach 2:
The common clock divider acts as an intermediary that generates a standardized reference clock signal and distributes it to all serializer circuits. This intermediary component ensures all lanes operate from a common timing reference, maintaining synchronization reliability without requiring complex direct clock distribution paths between individual lane components.
3Loss of time
If synchronization loss is not detected promptly, then system simplicity is maintained, but latency increases due to delayed transmission
Solution Approach 1:
The patent implements a feedback mechanism where each serializer circuit monitors the reference clock signal from the common clock divider and generates a status indication regarding synchronization status. This feedback loop enables prompt detection of synchronization loss conditions, allowing the system to respond quickly and maintain efficient data transmission without excessive latency.
Solution Approach 2:
The system performs preliminary synchronization checking by continuously monitoring the reference clock signal before data transmission occurs. This preliminary detection capability allows the system to identify synchronization loss conditions early, before they impact data transmission, enabling timely corrective action and minimizing latency.
Data Source
AI summary
A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits. Each serializer circuit generates a sampled sync loss signal by sampling the sync loss pulse in accordance with a parallel clock signal, and a Boolean value is assigned to the sampled sync loss signal and output. A logic block detects a sync loss when the sampled sync loss signal of any serializer circuit is out of sync from the sync loss pulse based on the Boolean value.