Serializing Transmitter With Pulse Multiplexing for Lower I/O Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-speed I/O data circuits face limitations in bandwidth and power efficiency due to design constraints such as inter-symbol interference and excessive power consumption, particularly in achieving reliable setup and hold time requirements at high data rates, and often require significant memory and latency, making them inadequate for optimal chip-to-chip communication.
Innovation Solution
A serializing transmitter design utilizing four pulse-toggled 2:1 CMOS multiplexers forming an 8:4 serialization stage followed by a pulse-controlled 4:1 serializer with push-pull output drivers, which consumes one-quarter the power of comparable parallel-terminated drivers, and features programmable source resistance and feedback control loops for optimal pulse width and alignment, minimizing power supply current and inter-symbol interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2:1 multiplexer is designed with sufficient bandwidth to avoid inter-symbol interference, then signal integrity is improved, but power consumption increases excessively
Solution Approach 1:
The patent divides the single high-bandwidth 2:1 multiplexer into multiple lower-bandwidth multiplexing stages (e.g., multiple 2:1 MUXes operating at half the data rate). Each multiplexer handles a portion of the data bits simultaneously, reducing the bandwidth requirement per device while maintaining overall signal integrity through parallel operation and interleaved data streams.
2Reliability
If the 2:1 multiplexer is sized to meet setup and hold time requirements at very high data rates, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent segments the high-speed data stream into multiple lower-rate parallel streams that are multiplexed in stages. Each multiplexer operates at a relaxed clock rate, allowing sufficient time for setup and hold requirements to be met without requiring excessively large or complex single-stage multiplexer designs.
Solution Approach 2:
The patent transitions from a single high-speed time dimension to multiple parallel lower-speed time dimensions. By distributing data across multiple lanes and clock phases, the system achieves high overall data rates while each individual multiplexer operates at manageable speeds that satisfy timing requirements.
3Adaptability or versatility
If conventional I/O circuits are used for chip-to-chip communication, then design flexibility is maintained, but bandwidth and power efficiency are insufficient
Solution Approach 1:
The patent implements dynamically adjustable parameters including programmable source resistance and configurable multiplexing ratios. The system can adapt its operating characteristics through feedback control loops that adjust pulse width, alignment, and drive strength to optimize performance for different data rates and channel conditions while maintaining flexible architecture.
Data Source
AI summary
In embodiments of a serializing transmitter, the serializing transmitter includes one or more multiplexing drive units that each generate a series of output pulses derived from input data signals and multi-phase clock signals. Each of the multiplexing drive units includes a pulse-controlled push-pull output driver that has first and second inputs, and an output coupled to an output of the multiplexing drive unit. Each of the multiplexing drive units also includes a first M:1 (where M is two or more) pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and generating a first series of intermediate pulses at the output; and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, and generating a second series of intermediate pulses at the output.