Serially Connected Enhancement and Depletion Mode HFETs
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Solution Overview
Problem
Conventional heterojunction field effect transistors (HFETs) face challenges in combining normally off and normally on devices using different materials in a single fabrication process, which is complex and expensive, and there is a need for a streamlined process to form a normally off device serially connected to a normally on device for power electronics applications.
Innovation Solution
The development of an HFET device with a gate controlling a normally off channel region and a gate controlling a normally on channel region, utilizing a heterojunction field effect transistor with a first piezoelectric layer and a second piezoelectric layer, where the first gate controls a normally off segment and the second gate controls a normally on segment, both formed using the same III-V semiconductor materials to minimize fabrication differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different materials are used to form normally off and normally on devices, then device functionality is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent merges the functionality of normally off and normally on devices into a single heterostructure using the same III-V semiconductor material system. The normally off HFET and normally on HFET are integrated in series within the same AlGaAs/GaAs heterostructure, eliminating the need for separate fabrication processes for different material systems while maintaining both device functionalities.
Solution Approach 2:
The patent applies local quality by creating spatially varying doping profiles and aluminum composition gradients within the AlGaAs barrier layers. The normally off region uses undoped or lightly doped channels with specific aluminum compositions, while the normally on region uses differently doped channels, allowing both device types to coexist in the same material system with distinct local properties.
2Adaptability or versatility
If different materials are used to form normally off and normally on devices, then device functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines both normally off and normally on device functionalities into a single monolithic heterostructure fabricated in one process flow. This merging eliminates the need for separate epitaxial growth, photolithography, and metalization steps that would be required if different material systems were used, thereby reducing manufacturing cost.
Solution Approach 2:
The AlGaAs/GaAs heterostructure serves multiple functions simultaneously: it provides the high-electron-mobility channel for both normally off and normally on HFETs, acts as the barrier layer for heterostructure formation, and enables both enhancement-mode and depletion-mode operation through appropriate doping and composition design.
3Power
If a normally on device is used, then high current conduction is achieved, but safety and energy conversion efficiency decrease due to floating or grounded gate terminal failures
Solution Approach 1:
The patent segments the channel into distinct normally off and normally on regions that are serially connected. The normally off segment acts as a safety guard that blocks current flow when the gate is floating or grounded, preventing dangerous power conduction, while the normally on segment provides high current conduction capability when properly biased.
Solution Approach 2:
The normally off HFET is positioned upstream in the series connection to preemptively block current flow in the event of gate terminal failure. This preliminary protective action prevents the normally on HFET from conducting hazardous currents, thereby ensuring safety before a failure condition can propagate through the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of a high-voltage device with positive pinch-off voltage and high breakdown voltage, while minimizing fabrication complexities and costs by using the same materials for both normally off and normally on segments, enhancing safety and energy conversion efficiency in power electronics.
Implementation Method 1
stress in the dielectric layer creates a piezoelectric charge of at least about 1×10^11 per cm^2 of electronic charge in the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap
Data Source
AI summary
Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.