Series-Connected RAMs with Shared Test Circuit
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Solution Overview
Problem
Existing semiconductor circuits with built-in self-test (BIST) circuits face challenges in efficiently testing multiple memory units due to increased chip size and reduced wiring flexibility caused by the need for separate test circuits and signal paths for each memory unit.
Innovation Solution
A semiconductor circuit design where multiple RAMs are connected in series, sharing a common test circuit and comparison circuit, allowing for reduced chip size and improved wiring flexibility by using a single test circuit for multiple RAMs, and enabling individual defective address identification through adjustable defective address information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test circuits and signal paths are provided for each memory unit, then test coverage and reliability are improved, but chip size increases and wiring flexibility decreases
Solution Approach 1:
The patent merges multiple separate test circuits into a single shared test circuit that can sequentially test multiple memory units. The test circuit is connected to all memory units through a common bus structure, allowing one test circuit to perform testing functions for multiple memory units by switching between them, thereby reducing the overall chip area while maintaining comprehensive test coverage.
Solution Approach 2:
The test circuit is designed with multi-functionality to serve multiple memory units. It can be configured to test different memory units by receiving control signals that route the test signals appropriately. This universal test circuit performs the same testing functions for each memory unit, eliminating the need for dedicated test circuits for each unit and reducing chip size.
2Measurement precision
If separate test circuits are provided for each memory unit, then test precision is improved, but device complexity increases
Solution Approach 1:
Multiple separate test circuits are merged into a single shared test circuit that sequentially serves multiple memory units. This consolidation reduces device complexity by eliminating redundant circuitry while maintaining test precision through proper signal routing and control mechanisms that ensure each memory unit receives appropriate test signals.
Solution Approach 2:
The test circuit incorporates dynamic control capabilities to switch between different memory units during testing. Control signals dynamically route test signals to the appropriate memory unit and direct output signals to the comparison circuit, enabling a single static circuit structure to perform dynamic testing of multiple units with high precision.
3Measurement precision
If separate signal paths are provided for each memory unit, then defect identification accuracy is improved, but wiring flexibility and chip area are reduced
Solution Approach 1:
A comparison circuit serves as an intermediary between the shared test circuit and multiple memory units. It receives output signals from any tested memory unit and compares them against expected values, enabling accurate defect identification. This intermediary structure maintains high defect identification accuracy while allowing flexible wiring arrangements since all memory units share common input and output paths through the comparison circuit.
Data Source
AI summary
According to one embodiment, a semiconductor circuit includes a plurality of memories. The memories are connected to one another in series such that an output node of the memory of the first stage is connected to an input node of the memory of the second stage. The semiconductor circuit includes a test circuit that outputs test data to an input node of the memory of the first stage among the plurality of memories, and a comparison circuit that compares data output from an output node of the memory of the final stage among the plurality of memories with expectation value data.