Series Continuous Time Linear Equalizers Using Passive LC Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional continuous time linear equalizers in double-data rate data buffer chips and registered clock driver chips face challenges in reducing power consumption, especially at high signal frequencies, with active designs consuming more power and passive RC-based designs experiencing process variation-induced filter response drifts, making calibration difficult.
Innovation Solution
Implementing a series of continuous time linear equalizers using passive LC-based circuits with inductors, which provide low power consumption, reduced sensitivity to process, temperature, and voltage variations, and improved timing performance, while incorporating LC tanks in clock paths to recycle signal energy and reduce clock amplitudes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional active designs are used for continuous time linear equalizers, then filtering performance is achieved, but power consumption increases as signal speeds increase
Solution Approach 1:
The patent replaces active amplifier-based filtering mechanisms with passive LC circuit filtering. The continuous time linear equalizer uses passive inductors and capacitors to achieve frequency-selective filtering without requiring active amplification, thereby eliminating the power consumption associated with active devices while maintaining filtering performance through resonant circuit behavior.
Solution Approach 2:
The patent changes the fundamental operating parameters by transitioning from active voltage amplification to passive resonant filtering. The equalizer operates by tuning the resonant frequency of LC circuits to match the signal frequency, using quality factor (Q) and impedance matching rather than gain amplification to achieve the desired filtering and equalization effects.
2Power
If conventional passive RC-based designs are used, then power consumption is reduced, but filter response drifts due to resistor process variation making calibration difficult
Solution Approach 1:
The patent employs composite LC circuit structures combining inductors and capacitors in resonant configurations. This composite approach replaces single-component RC circuits with multi-component resonant systems where the frequency response is determined by the square root of the product of L and C values, providing better tolerance to individual component variations and improved filter response stability.
Solution Approach 2:
The patent uses standard integrated circuit inductors and capacitors with typical process variations, avoiding the need for precision resistors. The resonant nature of LC circuits provides inherent insensitivity to component value variations, eliminating the need for complex calibration mechanisms while maintaining stable filter response.
3Power
If passive RC-based designs are used, then power consumption is lower, but calibration complexity increases due to filter response drift
Solution Approach 1:
The patent implements self-tuning LC resonant circuits that automatically maintain their resonant frequency through the natural physics of inductor-capacitor interaction. The circuits self-adjust to signal frequency through resonant coupling and impedance matching mechanisms, eliminating the need for external calibration procedures while consuming minimal power.
Solution Approach 2:
The patent employs feedback mechanisms where the output of the LC resonant circuit feeds back to adjust the input coupling and impedance matching. This automatic feedback regulation maintains optimal filter response without requiring manual calibration, as the circuit self-corrects for component variations through its resonant behavior and feedback control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low power performance, improved timing accuracy, and reduced latency, effectively addressing the power consumption and calibration challenges of conventional designs by leveraging the stability and quality factor of inductors over resistors in integrated circuits.
Implementation Method 1
The first continuous time linear equalizer circuit may be configured to generate an intermediate signal by filtering an input signal using a first passive bandpass filter having an inductor
Implementation Method 2
incorporating LC tanks in clock paths to recycle signal energy and reduce clock amplitudes
Data Source
AI summary
An apparatus includes a first continuous time linear equalizer circuit and a second continuous time linear equalizer circuit. The first continuous time linear equalizer circuit may be configured to generate an intermediate signal by filtering an input signal using a first passive bandpass filter having an inductor. The second continuous time linear equalizer circuit may be configured to generate an output signal by filtering the intermediate signal.