Series-Connected FET Biasing for High-Voltage Linear Operation
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Solution Overview
Problem
High power semiconductor switching devices face challenges with thermal instability and high cost when operating in active linear mode, particularly at high voltages, due to the use of expensive linear MOSFETs which have high on-resistance and limited Forward-bias Safe Operating Area (FSOA).
Innovation Solution
Connecting multiple semiconductor switch devices, such as FETs, in series with a network of gate bias resistances to balance voltage and thermal load, allowing feedback control of gate-to-source voltage to regulate current across all devices, thereby enabling operation at higher voltages and currents while avoiding thermal instability and reducing costs by using lower-cost commercially available switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If expensive linear MOSFETs are used for high voltage operation in active linear mode, then voltage handling capability is improved, but cost increases and thermal instability occurs
Solution Approach 1:
The patent divides a single high-voltage device into multiple lower-voltage FETs connected in series. Each FET handles a portion of the total voltage, allowing the system to achieve high voltage capability while using reliable, lower-voltage components that operate within their safe operating areas, thereby improving thermal stability and reducing cost.
Solution Approach 2:
The patent changes the operating parameters by using multiple devices in series rather than a single device. This distributes the voltage stress and thermal load across multiple components, allowing each FET to operate at lower, more stable parameters while collectively achieving the required high voltage handling capability.
2Stability of the object's composition
If multiple FETs are connected in series with gate bias resistors to balance voltage, then voltage and thermal load distribution is improved, but device complexity increases
Solution Approach 1:
The patent introduces gate bias resistors as intermediary components connected to the gates of each FET. These resistors automatically balance the voltage distribution across the series-connected FETs by providing a voltage division network, eliminating the need for complex active control circuits while achieving stable voltage and thermal load distribution.
Solution Approach 2:
The gate bias resistor network provides self-service voltage balancing across the FETs. The resistors automatically adjust the gate voltages to distribute the total voltage evenly across all series-connected devices based on their inherent resistance values, creating a self-regulating system that maintains stability without external intervention.
3Productivity
If a single high-voltage switch device is used, then device count is reduced, but current handling capability and thermal load capacity are limited
Solution Approach 1:
The patent segments the current handling function across multiple parallel-connected FETs. Each FET contributes to the total current capacity, allowing the system to achieve higher current handling capability and thermal load capacity by combining multiple devices rather than relying on a single high-voltage device with limited current capacity.
Data Source
AI summary
The addition of gate bias resistors substantially balances the voltage across any number of series-connected FETs, while the feedback control of the gate-source voltage of one FET controls the current through all of the FETs. In this way, the thermal load and voltage stress are substantially balanced for series connected FETs operating in active linear mode (partially on), enabling operation at voltages much higher than the individual ratings of low cost, readily available FETs. Alternatively, series-connecting FETs for active-mode operation is thermally equivalent to paralleling because the FET heat load is practically uniform, enabling operation at much higher current. This concept is extended to a series connection of FETs that can block, pass, and/or limit alternating load current with the voltage applied across all the FETs being either polarity or alternating polarity. We provide analysis, practical design considerations, and simulation results.