Series-Powered Hash Board PCB Layout for Variable Chip Ranks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing series power supply circuits for serially connected computing chips face inefficiencies due to the need for multiple voltage domains and the requirement of different circuit configurations for chips of varying ranks, leading to complex and costly PCB designs.
Innovation Solution
A method where m layers of to-be-powered chips are connected in series between a power supply positive and negative electrode on a hash board, with the highest-layer chips connected to the positive and bottommost-layer chips to the negative, allowing for a unified PCB design by replacing unnecessary layers with conductor patches, enabling efficient power supply and signal communication across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple voltage domains are used for serially connected IC chips, then power supply conversion efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a unified PCB structure that can accommodate different numbers of chip layers (m-n layers) through configurable conductor patches. The same PCB design serves multiple configurations, reducing the need for different PCB types while maintaining efficient series power supply architecture with multiple voltage domains.
Solution Approach 2:
The patent segments the power supply circuit into m layers of series-connected chips with distinct voltage domains. Each chip layer operates at a different voltage level, creating segmented voltage domains that improve power conversion efficiency by matching power supply voltages to actual chip operating requirements.
2Adaptability or versatility
If different circuit configurations are used for chips of varying ranks, then adaptability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements universality by creating a single standardized PCB design that can accommodate different chip ranks and configurations. By using configurable conductor patches that can be activated or deactivated based on the number of chip layers, the same PCB serves multiple purposes, eliminating the need for different PCB designs for different chip configurations.
Solution Approach 2:
The patent applies dynamics by making the circuit configuration adaptable through selective activation of conductor patches. The PCB design allows dynamic reconfiguration based on the actual number of chip layers installed, enabling the same hardware platform to adapt to different chip ranks without requiring different PCB designs.
3Loss of energy
If m-n layers of chips are used in series, then power supply efficiency is improved, but PCB design complexity increases
Solution Approach 1:
The patent resolves this contradiction by designing a universal PCB that handles variable numbers of chip layers (m-n layers) through configurable conductor patches. The same PCB design maintains efficient series power supply architecture regardless of the actual number of chips installed, eliminating the need for complex custom PCB designs for each configuration.
Solution Approach 2:
The patent uses copying by replicating standard circuit patterns and conductor patch configurations across the PCB design. Instead of creating unique PCB layouts for different chip configurations, the same standardized patterns are copied and selectively activated, simplifying the PCB design process while maintaining efficiency.
Data Source
AI summary
A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.