Series Sub-Light-Emitting Chip Layout for LED Droop Reduction
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Solution Overview
Problem
Conventional light-emitting diodes (LEDs) face a significant droop effect at high current densities, leading to decreased emitting efficiency, which affects the performance of Mini LED modules used in backlight and display applications.
Innovation Solution
A light-emitting chip design featuring multiple sub-light-emitting chips connected in series, with each chip comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer, arranged in configurations such as rectangles or triangles on a base substrate, and connected via electrodes and insulating layers to enhance light-emitting efficiency and reduce current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single conventional light-emitting chip operates at high current density to obtain large optical power, then the optical power output increases, but the device efficiency suffers from serious droop effect leading to decreased emitting efficiency
Solution Approach 1:
The patent divides a single light-emitting chip into multiple sub-chips (e.g., three sub-chips) connected in series. Each sub-chip operates at lower current density while the series connection maintains high voltage operation, thereby achieving high optical power output without suffering from droop effect that plagues single high-current-density chips. This segmentation resolves the contradiction by allowing each segment to operate in its efficient regime while the system as a whole delivers high power.
2Loss of energy
If multiple sub-light-emitting chips are connected in series to reduce current density and improve emitting efficiency, then the emitting efficiency improves, but the device complexity increases due to additional electrodes and interconnections
Solution Approach 1:
The patent merges multiple sub-chips onto a single substrate with integrated electrode structures. The series connection is achieved through shared electrodes where the anode of one sub-chip serves as the cathode of the next, eliminating the need for separate external connections. This merging approach reduces structural complexity while maintaining the series connection benefits for improved emitting efficiency.
Solution Approach 2:
The electrodes in the patent serve dual functions: they act as both the anode for one sub-chip and the cathode for the adjacent sub-chip. This multi-functionality reduces the total number of electrodes required compared to having separate electrodes for each sub-chip, thereby simplifying the overall device structure while maintaining series connection operation.
3Loss of energy
If multiple sub-light-emitting chips are arranged on a base substrate to form series groups, then the light-emitting efficiency improves, but the manufacturing precision requirements increase due to alignment and connection accuracy
Solution Approach 1:
The patent employs preliminary patterning of the substrate and semiconductor layers before dividing into sub-chips. By pre-establishing the electrode patterns and semiconductor layer structures that will become multiple sub-chips, the alignment and connection accuracy is ensured during the fabrication process. This preliminary action approach reduces manufacturing precision requirements compared to attempting to align and connect pre-fabricated separate chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves light-emitting efficiency, reduces power consumption by approximately 50%, and enhances heat dissipation, leading to increased brightness uniformity and competitiveness in display devices.
Implementation Method 1
each sub-light-emitting chip includes a first semiconductor layer, a second semiconductor layer and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer
Data Source
AI summary
A light-emitting chip and a light-emitting substrate are provided. The light-emitting chip includes a base substrate and at least two sub-light-emitting chips disposed on a side of the base substrate, wherein each sub-light-emitting chip includes a first semiconductor layer, a second semiconductor layer and an light-emitting layer located between the first semiconductor layer and the second semiconductor layer which are stacked.